[llvm] r277601 - [Hexagon] Do not check alignment for unsized types in isLegalAddressingMode

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Aug  3 10:06:18 2016
New Revision: 277601

URL: http://llvm.org/viewvc/llvm-project?rev=277601&view=rev
Log:
[Hexagon] Do not check alignment for unsized types in isLegalAddressingMode

When the same base address is used to load two different data types, LSR
would assume a memory type of "void". This type is not sized and has no
alignment information. Checking for it causes a crash.

Added:
    llvm/trunk/test/CodeGen/Hexagon/is-legal-void.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=277601&r1=277600&r2=277601&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Aug  3 10:06:18 2016
@@ -3055,13 +3055,22 @@ bool HexagonTargetLowering::isFPImmLegal
 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                                   const AddrMode &AM, Type *Ty,
                                                   unsigned AS) const {
-  unsigned A = DL.getABITypeAlignment(Ty);
-  // The base offset must be a multiple of the alignment.
-  if ((AM.BaseOffs % A) != 0)
-    return false;
-  // The shifted offset must fit in 11 bits.
-  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
-    return false;
+  if (Ty->isSized()) {
+    // When LSR detects uses of the same base address to access different
+    // types (e.g. unions), it will assume a conservative type for these
+    // uses:
+    //   LSR Use: Kind=Address of void in addrspace(4294967295), ...
+    // The type Ty passed here would then be "void". Skip the alignment
+    // checks, but do not return false right away, since that confuses
+    // LSR into crashing.
+    unsigned A = DL.getABITypeAlignment(Ty);
+    // The base offset must be a multiple of the alignment.
+    if ((AM.BaseOffs % A) != 0)
+      return false;
+    // The shifted offset must fit in 11 bits.
+    if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
+      return false;
+  }
 
   // No global is ever allowed as a base.
   if (AM.BaseGV)

Added: llvm/trunk/test/CodeGen/Hexagon/is-legal-void.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/is-legal-void.ll?rev=277601&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/is-legal-void.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/is-legal-void.ll Wed Aug  3 10:06:18 2016
@@ -0,0 +1,58 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+; The two loads based on %struct.0, loading two different data types
+; cause LSR to assume type "void" for the memory type. This would then
+; cause an assert in isLegalAddressingMode. Make sure we no longer crash.
+
+target triple = "hexagon"
+
+%struct.0 = type { i8*, i8, %union.anon.0 }
+%union.anon.0 = type { i8* }
+
+define hidden fastcc void @fred() unnamed_addr #0 {
+entry:
+  br i1 undef, label %while.end, label %while.body.lr.ph
+
+while.body.lr.ph:                                 ; preds = %entry
+  br label %while.body
+
+while.body:                                       ; preds = %exit.2, %while.body.lr.ph
+  %lsr.iv = phi %struct.0* [ %cgep22, %exit.2 ], [ undef, %while.body.lr.ph ]
+  switch i32 undef, label %exit [
+    i32 1, label %sw.bb.i
+    i32 2, label %sw.bb3.i
+  ]
+
+sw.bb.i:                                          ; preds = %while.body
+  unreachable
+
+sw.bb3.i:                                         ; preds = %while.body
+  unreachable
+
+exit:                                             ; preds = %while.body
+  switch i32 undef, label %exit.2 [
+    i32 1, label %sw.bb.i17
+    i32 2, label %sw.bb3.i20
+  ]
+
+sw.bb.i17:                                        ; preds = %.exit
+  %0 = bitcast %struct.0* %lsr.iv to i32*
+  %1 = load i32, i32* %0, align 4
+  unreachable
+
+sw.bb3.i20:                                       ; preds = %exit
+  %2 = bitcast %struct.0* %lsr.iv to i8**
+  %3 = load i8*, i8** %2, align 4
+  unreachable
+
+exit.2:                                           ; preds = %exit
+  %cgep22 = getelementptr %struct.0, %struct.0* %lsr.iv, i32 1
+  br label %while.body
+
+while.end:                                        ; preds = %entry
+  ret void
+}
+
+attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
+