[PATCH] D23067: TargetInstrInfo: add two new target hooks to analyse branch offsets

Sjoerd Meijer via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 3 03:29:07 PDT 2016


SjoerdMeijer updated this revision to Diff 66633.
SjoerdMeijer added a comment.

I have changed the function name and its arguments. For consistency, I changed the other function to have the same arguments.

Regarding the overlap: I understand things a bit better now. You mentioned that you want to  "optimize the branch relaxation pass by reordering and duplicating blocks to avoid long expansions", which I think is exactly the same I am trying to achieve. I was focusing on ARM codegen and thus the ARM backend, and was actually not aware of this AArch64 BranchRelaxation backend pass. :-( There are quite a bit of utility functions in there that I was implementing as well, so I will be looking into factoring some of this out. I was making my chances in codegen pass MachineBlockPlacement, which runs before the target specific passes. As far as I understand now, AArch64 BranchRelaxation is making changes for legality reasons: if the displacement of conditional branches is out of range, it creates a conditional branch with the inverse condition, followed by an unconditional branch. If you want to optimise branch distances (create short branches), then MachineBlockPlacement might look like a better place, which is what I was doing and thus we might be working on the same things. Let me know if we need to further synchronise on this.


https://reviews.llvm.org/D23067

Files:
  include/llvm/Target/TargetInstrInfo.h
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h

Index: lib/Target/ARM/ARMBaseInstrInfo.h
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.h
+++ lib/Target/ARM/ARMBaseInstrInfo.h
@@ -120,6 +120,8 @@
                                      const ScheduleDAG *DAG) const override;
 
   // Branch analysis.
+  bool isBranchOffsetInRange(MachineInstr &MI, int64_t Offset) const override;
+  int optimizeShortBranch(MachineInstr &MI, int64_t Offset) const override;
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -290,6 +290,31 @@
 }
 
 // Branch analysis.
+bool ARMBaseInstrInfo::isBranchOffsetInRange(MachineInstr &MI,
+                                             int64_t Offset) const {
+  switch (MI.getOpcode()) {
+    case ARM::tBcc:
+      if (Offset < -256 || Offset > 254)
+        return false;
+    case ARM::tB:
+      if (Offset < -2048 || Offset > 2046)
+        return false;
+  }
+  return true;
+}
+
+// Map branch instructions to Thumb1 equivalent branches.
+int ARMBaseInstrInfo::optimizeShortBranch(MachineInstr &MI,
+                                          int64_t Offset) const {
+  switch (MI.getOpcode()) {
+  case ARM::t2B:
+    return ARM::tB;
+  case ARM::t2Bcc:
+    return ARM::tBcc;
+  }
+  return -1;
+}
+
 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                      MachineBasicBlock *&TBB,
                                      MachineBasicBlock *&FBB,
Index: include/llvm/Target/TargetInstrInfo.h
===================================================================
--- include/llvm/Target/TargetInstrInfo.h
+++ include/llvm/Target/TargetInstrInfo.h
@@ -480,6 +480,18 @@
     return true;
   }
 
+  /// Return true if the offset is in range of the branch instruction and
+  /// false otherwise.
+  virtual bool isBranchOffsetInRange(MachineInstr &MI, int64_t Offset) const {
+    return true;
+  }
+
+  /// Return the opcode if there exist a branch instruction with a smaller
+  /// encoding, or -1 otherwise.
+  virtual int optimizeShortBranch(MachineInstr &MI, int64_t Offset) const {
+    return -1;
+  }
+
   /// Represents a predicate at the MachineFunction level.  The control flow a
   /// MachineBranchPredicate represents is:
   ///


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