[PATCH] D23002: DAGCombiner: check isZExtFree before doing combine

[Matt Arsenault via llvm-commits]

arsenm added a comment.

AMDGPU wants this, it eliminates a 64-bit shift. This will make even more sense when i16 is added as a legal type for some subtargets

define void @foo(i64 addrspace(1)* %out, i16 %x) {

  %zext0 = zext i16 %x to i32
  %shl = shl i32 %zext0, 11
  %zext1 = zext i32 %shl to i64
  store i64 %zext1, i64 addrspace(1)* %out
  ret void

}


Repository:
  rL LLVM

https://reviews.llvm.org/D23002