[llvm] r277477 - [GlobalISel] Set and require RegBankSelected MF property.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 2 09:17:18 PDT 2016
Author: ab
Date: Tue Aug 2 11:17:18 2016
New Revision: 277477
URL: http://llvm.org/viewvc/llvm-project?rev=277477&view=rev
Log:
[GlobalISel] Set and require RegBankSelected MF property.
The InstructionSelect pass assumes that RegBankSelect ran; set the
property on all tests (thereby verifying the test inputs) and require
it in the pass.
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelect.h?rev=277477&r1=277476&r2=277477&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelect.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelect.h Tue Aug 2 11:17:18 2016
@@ -33,7 +33,8 @@ public:
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties()
.set(MachineFunctionProperties::Property::IsSSA)
- .set(MachineFunctionProperties::Property::Legalized);
+ .set(MachineFunctionProperties::Property::Legalized)
+ .set(MachineFunctionProperties::Property::RegBankSelected);
}
InstructionSelect();
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegBankSelect.h?rev=277477&r1=277476&r2=277477&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegBankSelect.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegBankSelect.h Tue Aug 2 11:17:18 2016
@@ -590,6 +590,11 @@ public:
.set(MachineFunctionProperties::Property::Legalized);
}
+ MachineFunctionProperties getSetProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::RegBankSelected);
+ }
+
/// Walk through \p MF and assign a register bank to every virtual register
/// that are still mapped to nothing.
/// The target needs to provide a RegisterBankInfo and in particular
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=277477&r1=277476&r2=277477&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Tue Aug 2 11:17:18 2016
@@ -40,6 +40,7 @@
name: add_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
@@ -65,6 +66,7 @@ body: |
name: add_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
@@ -90,6 +92,7 @@ body: |
name: sub_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
@@ -115,6 +118,7 @@ body: |
name: sub_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
@@ -140,6 +144,7 @@ body: |
name: or_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
@@ -165,6 +170,7 @@ body: |
name: or_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
@@ -190,6 +196,7 @@ body: |
name: xor_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
@@ -215,6 +222,7 @@ body: |
name: xor_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
@@ -240,6 +248,7 @@ body: |
name: and_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
@@ -265,6 +274,7 @@ body: |
name: and_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
@@ -289,6 +299,7 @@ body: |
name: unconditional_br
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: body:
# CHECK: bb.0:
@@ -306,6 +317,7 @@ body: |
name: load_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
@@ -331,6 +343,7 @@ body: |
name: load_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
@@ -356,6 +369,7 @@ body: |
name: store_s64_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
@@ -383,6 +397,7 @@ body: |
name: store_s32_gpr
isSSA: true
legalized: true
+regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=277477&r1=277476&r2=277477&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Tue Aug 2 11:17:18 2016
@@ -56,6 +56,8 @@
}
define void @ignoreTargetSpecificInst() { ret void }
+
+ define void @regBankSelected_property() { ret void }
...
---
@@ -365,3 +367,17 @@ body: |
%x0 = COPY %1
RET_ReallyLR implicit %x0
...
+
+---
+# Check that we set the "regBankSelected" property.
+# CHECK-LABEL: name: regBankSelected_property
+# CHECK: legalized: true
+# CHECK: regBankSelected: true
+# CHECK: isSSA: true
+name: regBankSelected_property
+isSSA: true
+legalized: true
+regBankSelected: false
+body: |
+ bb.0:
+...
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