[PATCH] D23000: [X86] Improve 64-bit shifts on 32-bit targets (PR14593)

[Simon Pilgrim via llvm-commits]

RKSimon added a comment.

Thanks Eli.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:28679
@@ +28678,3 @@
+        }
+        // Test for ADD( Y, Y ) as an equivalent to SHL( Y, 1 ).
+        if (InnerShift == ISD::SHL && Op1.getOpcode() == ISD::ADD &&
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eli.friedman wrote:
> If DAGCombine doesn't transform Y+Y to Y<<1, it should.  (instcombine definitely does this.)  Not really important for now, though.
In the old codegen we were seeing code like 'leal (%edx,%edx), %eax' being lowered from shl( v, 1 ) IR.


Repository:
  rL LLVM

https://reviews.llvm.org/D23000