[llvm] r277280 - Strip trailing whitespace

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sat Jul 30 13:53:21 PDT 2016


Author: rksimon
Date: Sat Jul 30 15:53:21 2016
New Revision: 277280

URL: http://llvm.org/viewvc/llvm-project?rev=277280&view=rev
Log:
Strip trailing whitespace

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=277280&r1=277279&r2=277280&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jul 30 15:53:21 2016
@@ -26452,9 +26452,9 @@ static SDValue combineBasicSADPattern(SD
   // in the SAD vector.
   unsigned Stages = Log2_32(VT.getVectorNumElements());
   MVT SadVT = SAD.getSimpleValueType();
-  if (Stages > 3) {    
+  if (Stages > 3) {
     unsigned SadElems = SadVT.getVectorNumElements();
-    
+
     for(unsigned i = Stages - 3; i > 0; --i) {
       SmallVector<int, 16> Mask(SadElems, -1);
       for(unsigned j = 0, MaskEnd = 1 << (i - 1); j < MaskEnd; ++j)
@@ -26465,11 +26465,10 @@ static SDValue combineBasicSADPattern(SD
       SAD = DAG.getNode(ISD::ADD, DL, SadVT, SAD, Shuffle);
     }
   }
-  
 
   // Return the lowest i32.
-  MVT ResVT = MVT::getVectorVT(MVT::i32, SadVT.getSizeInBits() / 32);  
-  SAD = DAG.getNode(ISD::BITCAST, DL, ResVT, SAD);  
+  MVT ResVT = MVT::getVectorVT(MVT::i32, SadVT.getSizeInBits() / 32);
+  SAD = DAG.getNode(ISD::BITCAST, DL, ResVT, SAD);
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, SAD,
                      Extract->getOperand(1));
 }
@@ -30868,7 +30867,7 @@ static SDValue combineLoopSADPattern(SDN
 
   // We only handle v16i32 for SSE2 / v32i32 for AVX2 / v64i32 for AVX512.
   // TODO: We should be able to handle larger vectors by splitting them before
-  // feeding them into several SADs, and then reducing over those.  
+  // feeding them into several SADs, and then reducing over those.
   if (VT.getSizeInBits() / 4 > RegSize)
     return SDValue();
 




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