[PATCH] D22933: DAG: avoid truncating a sign extended operand when test equality against zero

[Eli Friedman via llvm-commits]

eli.friedman added a comment.

It would be nice to have a couple testcases involving numbers which aren't zero.


================
Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:956
@@ -955,3 +955,3 @@
         OpR->getOpcode() == ISD::AssertSext &&
         cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
       NewLHS = OpL;
----------------
This check is now unnecessary.

================
Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:964
@@ +963,3 @@
+                       DAG.ComputeNumSignBits(OpR) + 1 <=
+                   NewRHS.getValueType().getSizeInBits()) {
+      // If the width of OpL/OpR excluding the same sign bits is no greater than
----------------
Maybe reorganize this a bit to make it more readable?  A couple variables might be helpful.


Repository:
  rL LLVM

https://reviews.llvm.org/D22933