[llvm] r277173 - [AArch64][GlobalISel] Select G_XOR.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Fri Jul 29 11:56:25 2016
New Revision: 277173

URL: http://llvm.org/viewvc/llvm-project?rev=277173&view=rev
Log:
[AArch64][GlobalISel] Select G_XOR.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=277173&r1=277172&r2=277173&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Fri Jul 29 11:56:25 2016
@@ -52,6 +52,8 @@ static unsigned selectBinaryOp(unsigned
       switch (GenericOpc) {
       case TargetOpcode::G_OR:
         return AArch64::ORRWrr;
+      case TargetOpcode::G_XOR:
+        return AArch64::EORWrr;
       case TargetOpcode::G_AND:
         return AArch64::ANDWrr;
       case TargetOpcode::G_ADD:
@@ -65,6 +67,8 @@ static unsigned selectBinaryOp(unsigned
       switch (GenericOpc) {
       case TargetOpcode::G_OR:
         return AArch64::ORRXrr;
+      case TargetOpcode::G_XOR:
+        return AArch64::EORXrr;
       case TargetOpcode::G_AND:
         return AArch64::ANDXrr;
       case TargetOpcode::G_ADD:
@@ -166,6 +170,7 @@ bool AArch64InstructionSelector::select(
   }
 
   case TargetOpcode::G_OR:
+  case TargetOpcode::G_XOR:
   case TargetOpcode::G_AND:
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB: {

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=277173&r1=277172&r2=277173&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Fri Jul 29 11:56:25 2016
@@ -17,6 +17,9 @@
   define void @or_s32_gpr() { ret void }
   define void @or_s64_gpr() { ret void }
 
+  define void @xor_s32_gpr() { ret void }
+  define void @xor_s64_gpr() { ret void }
+
   define void @and_s32_gpr() { ret void }
   define void @and_s64_gpr() { ret void }
 
@@ -176,6 +179,54 @@ body:             |
 ...
 
 ---
+# Same as add_s32_gpr, for G_XOR operations.
+# CHECK-LABEL: name: xor_s32_gpr
+name:            xor_s32_gpr
+isSSA:           true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = EORWrr %0, %0
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(32) = COPY %w0
+    %1(32) = G_XOR s32 %0, %0
+...
+
+---
+# Same as add_s64_gpr, for G_XOR operations.
+# CHECK-LABEL: name: xor_s64_gpr
+name:            xor_s64_gpr
+isSSA:           true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = EORXrr %0, %0
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0(64) = COPY %x0
+    %1(64) = G_XOR s64 %0, %0
+...
+
+---
 # Same as add_s32_gpr, for G_AND operations.
 # CHECK-LABEL: name: and_s32_gpr
 name:            and_s32_gpr