[PATCH] D22933: DAG: avoid truncating a sign extended operand when test equality against zero

[Eli Friedman via llvm-commits]

eli.friedman added a subscriber: eli.friedman.

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Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:964
@@ -955,3 +963,3 @@
         OpR->getOpcode() == ISD::AssertSext &&
         cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
       NewLHS = OpL;
----------------
Could you just use `OpL->ComputeNumSignBits() > ExtensionBits && OpR->ComputeNumSignBits() > ExtensionBits` or something like that here?


Repository:
  rL LLVM

https://reviews.llvm.org/D22933