[llvm] r276257 - AMDGPU: Fix phis from blocks split due to register indexing

[Hans Wennborg via llvm-commits]

On Thu, Jul 28, 2016 at 4:46 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
>> On Jul 28, 2016, at 16:34, Hans Wennborg via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>
>> I tried to merge this one, but the part below of the diff doesn't
>> apply since the branch doesn't have r275934.
>>
>> @@ -1161,7 +1166,7 @@ static void emitLoadM0FromVGPRLoop(const
>>   // Compare the just read M0 value to all possible Idx values.
>>   BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
>>     .addReg(CurrentIdxReg)
>> -    .addOperand(IdxReg);
>> +    .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
>>
>>   // Move index from VCC into M0
>>   if (Offset == 0) {
>> @@ -1232,6 +1237,8 @@ static MachineBasicBlock *loadM0FromVGPR
>>   MF->insert(MBBI, LoopBB);
>>   MF->insert(MBBI, RemainderBB);
>>
>> +  replaceSuccessorPhisWith(MBB, *RemainderBB);
>> +
>
> I thought the branch was after r275934? If r275934 isn’t in the branch then it shouldn’t be necessary

Nope, the branch was at r275826. I'll take this off the list, then :-)

Cheers,
Hans