[llvm] r277000 - [AArch64][GlobalISel] Remove 'alignment' from MIR tests. NFC.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Thu Jul 28 11:58:21 2016
New Revision: 277000

URL: http://llvm.org/viewvc/llvm-project?rev=277000&view=rev
Log:
[AArch64][GlobalISel] Remove 'alignment' from MIR tests. NFC.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=277000&r1=276999&r2=277000&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Thu Jul 28 11:58:21 2016
@@ -21,7 +21,6 @@
 # Also check that we constrain the register class of the COPY to GPR32.
 # CHECK-LABEL: name: add_s32_gpr
 name:            add_s32_gpr
-alignment:       2
 isSSA:           true
 
 # CHECK:      registers:
@@ -46,7 +45,6 @@ body:             |
 # Same as add_s32_gpr, for 64-bit operations.
 # CHECK-LABEL: name: add_s64_gpr
 name:            add_s64_gpr
-alignment:       2
 isSSA:           true
 
 # CHECK:      registers:
@@ -71,7 +69,6 @@ body:             |
 # Same as add_s32_gpr, for G_OR operations.
 # CHECK-LABEL: name: or_s32_gpr
 name:            or_s32_gpr
-alignment:       2
 isSSA:           true
 
 # CHECK:      registers:
@@ -96,7 +93,6 @@ body:             |
 # Same as add_s64_gpr, for G_OR operations.
 # CHECK-LABEL: name: or_s64_gpr
 name:            or_s64_gpr
-alignment:       2
 isSSA:           true
 
 # CHECK:      registers: