[llvm] r276736 - [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 26 02:13:47 PDT 2016
Author: sdardis
Date: Tue Jul 26 04:13:46 2016
New Revision: 276736
URL: http://llvm.org/viewvc/llvm-project?rev=276736&view=rev
Log:
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases
Add the instruction alias sgtu (register form only), two operand forms of
s[rl]l and sra, and missing single/two operand forms of dnegu/neg.
Reviewers: dsanders
Differential Revision: https://reviews.llvm.org/D22752
Modified:
llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td Tue Jul 26 04:13:46 2016
@@ -506,11 +506,11 @@ def : MipsInstAlias<"dneg $rt, $rs",
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dneg $rt",
- (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
+ (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dnegu $rt",
- (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
+ (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MICROMIPS64R6;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue Jul 26 04:13:46 2016
@@ -1095,6 +1095,18 @@ let Predicates = [InMicroMips] in {
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+ def : MipsInstAlias<
+ "sgt $rd, $rs, $rt",
+ (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
+ "sgt $rs, $rt",
+ (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
+ "sgtu $rd, $rs, $rt",
+ (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
+ "sgtu $rs, $rt",
+ (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"slt $rs, $rt, $imm",
(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
simm32_relaxed:$imm), 0>;
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Jul 26 04:13:46 2016
@@ -668,11 +668,14 @@ let AdditionalPredicates = [NotInMicroMi
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dneg $rt",
- (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
+ (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
+ def : MipsInstAlias<"dnegu $rt",
+ (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
+ ISA_MIPS3;
}
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jul 26 04:13:46 2016
@@ -2233,12 +2233,26 @@ def : MipsInstAlias<"jalr $rs", (JALR RA
def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
def : MipsInstAlias<"neg $rt, $rs",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
-def : MipsInstAlias<"negu $rt",
- (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"neg $rt",
+ (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
+def : MipsInstAlias<"negu $rt",
+ (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<
+ "sgt $rd, $rs, $rt",
+ (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
+ "sgt $rs, $rt",
+ (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
+ "sgtu $rd, $rs, $rt",
+ (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
+ "sgtu $$rs, $rt",
+ (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<
"slt $rs, $rt, $imm",
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
@@ -2324,6 +2338,12 @@ let AdditionalPredicates = [NotInMicroMi
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+ def : MipsInstAlias<"sll $rd, $rt",
+ (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+ def : MipsInstAlias<"sra $rd, $rt",
+ (SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+ def : MipsInstAlias<"srl $rd, $rt",
+ (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
}
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync",
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue Jul 26 04:13:46 2016
@@ -86,6 +86,11 @@
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0x85,0x20,0x90]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x50]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Tue Jul 26 04:13:46 2016
@@ -47,6 +47,11 @@ a:
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0x85,0x20,0x90]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x50]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Tue Jul 26 04:13:46 2016
@@ -77,6 +77,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -86,7 +88,12 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
sb $s6,-19857($14)
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -96,10 +103,12 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Tue Jul 26 04:13:46 2016
@@ -97,6 +97,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -112,6 +114,11 @@ a:
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdc3 $12,5835($10)
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
@@ -124,10 +131,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Tue Jul 26 04:13:46 2016
@@ -157,6 +157,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -177,7 +179,12 @@ a:
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8)
sdr $11,-20423($12)
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -189,10 +196,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Tue Jul 26 04:13:46 2016
@@ -125,6 +125,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -142,7 +144,12 @@ a:
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -154,10 +161,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Tue Jul 26 04:13:46 2016
@@ -143,6 +143,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -177,7 +179,12 @@ a:
sdxc1 $f11,$10($14)
seb $25,$15
seh $v1,$12
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -189,10 +196,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Tue Jul 26 04:13:46 2016
@@ -143,6 +143,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -177,7 +179,12 @@ a:
sdxc1 $f11,$10($14)
seb $25,$15
seh $v1,$12
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -189,10 +196,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Tue Jul 26 04:13:46 2016
@@ -144,6 +144,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -178,7 +180,12 @@ a:
sdxc1 $f11,$10($14)
seb $25,$15
seh $v1,$12
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -190,10 +197,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Tue Jul 26 04:13:46 2016
@@ -126,6 +126,10 @@ a:
maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98]
msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99]
msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99]
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
+ negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
+ negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -177,6 +181,13 @@ a:
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Tue Jul 26 04:13:46 2016
@@ -179,6 +179,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -205,7 +207,12 @@ a:
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -217,10 +224,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Tue Jul 26 04:13:46 2016
@@ -180,6 +180,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -206,7 +208,12 @@ a:
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -218,10 +225,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Tue Jul 26 04:13:46 2016
@@ -196,6 +196,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -224,7 +226,12 @@ a:
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -236,10 +243,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Tue Jul 26 04:13:46 2016
@@ -212,6 +212,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -250,7 +252,12 @@ a:
sdxc1 $f11,$10($14)
seb $25,$15
seh $v1,$12
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -263,10 +270,12 @@ a:
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Tue Jul 26 04:13:46 2016
@@ -212,6 +212,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Tue Jul 26 04:13:46 2016
@@ -213,6 +213,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
@@ -251,7 +253,12 @@ a:
sdxc1 $f11,$10($14)
seb $25,$15
seh $v1,$12
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
@@ -264,10 +271,12 @@ a:
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=276736&r1=276735&r2=276736&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Tue Jul 26 04:13:46 2016
@@ -180,6 +180,10 @@ a:
muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9]
mul $2,$3,$4 # CHECK: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98]
mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99]
+ neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
+ neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
+ negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
+ negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# FIXME: Use the code generator in order to print the .set directives
@@ -203,6 +207,13 @@ a:
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
+ sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+ sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+ sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+ sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
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