[PATCH] D22752: [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases

Daniel Sanders via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 25 08:55:27 PDT 2016


dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

LGTM


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2329-2334
@@ -2314,2 +2328,8 @@
                       (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+  def : MipsInstAlias<"sll $rd, $rt",
+                      (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+  def : MipsInstAlias<"sra $rd, $rt",
+                      (SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+  def : MipsInstAlias<"srl $rd, $rt",
+                      (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
 }
----------------
It's a shame that InstAlias doesn't have the same TwoOperandAliasConstraint member that Instruction has. We wouldn't need to repeat ourselves as much if it did.


Repository:
  rL LLVM

https://reviews.llvm.org/D22752





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