[PATCH] D22726: [DAGCombine] Match shift amount by value rather than relying on common sub-expressions.

[bryant via llvm-commits]

bryant marked 2 inline comments as done.

================
Comment at: test/CodeGen/X86/cmp-zext-combine.ll:3
@@ +2,3 @@
+
+define i32 @nonzero(i32) {
+; CHECK-LABEL: nonzero:
----------------
Updated with the output of the python tool. I am not sure at all how to replicate this on i686, as the combine rules are different for zext i16 to i32.


Repository:
  rL LLVM

https://reviews.llvm.org/D22726