[PATCH] D22726: [DAGCombine] Match shift amount by value rather than relying on common sub-expressions.

[Simon Pilgrim via llvm-commits]

RKSimon added inline comments.

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4834
@@ -4831,2 +4833,3 @@
+          N1C->getZExtValue()) {
     unsigned BitSize = N0.getScalarValueSizeInBits();
     if (BitSize <= 64) {
----------------
Please regenerate the patch with context - something like

```
svn diff --diff-cmd=diff -x -U999999
```

================
Comment at: test/CodeGen/X86/cmp-zext-combine.ll:2
@@ +1,3 @@
+; RUN: llc -O3 -mtriple=x86_64 < %s | FileCheck %s
+
+define i32 @nonzero(i32) {
----------------
You shouldn't need the -O3

Please can you add a i686 test case as well, and use utils/update_llc_test_checks.py to generate full code output (you will need to add check prefixes to the 32/64 tests).


Repository:
  rL LLVM

https://reviews.llvm.org/D22726