[PATCH] D22708: TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG

[Matthias Braun via llvm-commits]

MatzeB created this revision.
MatzeB added reviewers: qcolombet, mkuper, t.p.northover.
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After some IRC discussion it became clear that the description/intention of this instruction is hard to understand.

Add a more verbose description and clarify the fact that this should not generate any code.

Repository:
  rL LLVM

https://reviews.llvm.org/D22708

Files:
  include/llvm/Target/TargetOpcodes.def

Index: include/llvm/Target/TargetOpcodes.def
===================================================================
--- include/llvm/Target/TargetOpcodes.def
+++ include/llvm/Target/TargetOpcodes.def
@@ -55,10 +55,14 @@
 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
 HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
 
-/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
-/// the first operand is an immediate integer constant. This constant is
-/// often zero, because it is commonly used to assert that the instruction
-/// defining the register implicitly clears the high bits.
+/// SUBREG_TO_REG - Assert the value of bits in a super register.
+/// The result of this instruction is the value of the second operand inserted
+/// into the subregister specified by the third operand.  All other bits are
+/// assumed to be equal to the bits in the immediate integer constant in the
+/// first operand.  This instruction just communicates information; No code
+/// should be generated.
+/// This is typically used after an instruction where the write to a subregister
+/// implicitly cleared the bits in the super registers.
 HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
 
 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain


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