[llvm] r276481 - GlobalISel: allow multiple types on MachineInstrs.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 22 16:47:19 PDT 2016
> On Jul 22, 2016, at 3:13 PM, Tim Northover via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: tnorthover
> Date: Fri Jul 22 17:13:36 2016
> New Revision: 276481
>
> URL: http://llvm.org/viewvc/llvm-project?rev=276481&view=rev
> Log:
> GlobalISel: allow multiple types on MachineInstrs.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/MachineInstr.h
> llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
> llvm/trunk/lib/CodeGen/MIRPrinter.cpp
> llvm/trunk/lib/CodeGen/MachineInstr.cpp
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
> llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
> llvm/trunk/test/CodeGen/MIR/X86/generic-virtual-registers.mir
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Jul 22 17:13:36 2016
> @@ -108,7 +108,7 @@ private:
> /// Type of the instruction in case of a generic opcode.
> /// \invariant This must be LLT{} if getOpcode() is not
> /// in the range of generic opcodes.
> - LLT Ty;
> + SmallVector<LLT, 1> Tys;
> #endif
>
> MachineInstr(const MachineInstr&) = delete;
> @@ -187,8 +187,9 @@ public:
>
> /// Set the type of the instruction.
> /// \pre getOpcode() is in the range of the generic opcodes.
> - void setType(LLT Ty);
> - LLT getType() const;
> + void setType(LLT Ty, unsigned Idx = 0);
> + LLT getType(int unsigned = 0) const;
> + unsigned getNumTypes() const;
>
> /// Return true if MI is in a bundle (but not the first MI in a bundle).
> ///
>
> Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Fri Jul 22 17:13:36 2016
> @@ -595,12 +595,17 @@ bool MIParser::parse(MachineInstr *&MI)
> if (Token.isError() || parseInstruction(OpCode, Flags))
> return true;
>
> - LLT Ty{};
> + SmallVector<LLT, 1> Tys;
> if (isPreISelGenericOpcode(OpCode)) {
> - // For generic opcode, a type is mandatory.
> - auto Loc = Token.location();
> - if (parseLowLevelType(Loc, Ty))
> - return true;
> + // For generic opcode, at least one type is mandatory.
> + expectAndConsume(MIToken::lbrace);
> + do {
> + auto Loc = Token.location();
> + Tys.resize(Tys.size() + 1);
> + if (parseLowLevelType(Loc, Tys[Tys.size() - 1]))
> + return true;
> + } while (consumeIfPresent(MIToken::comma));
> + expectAndConsume(MIToken::rbrace);
> }
>
> // Parse the remaining machine operands.
> @@ -658,8 +663,10 @@ bool MIParser::parse(MachineInstr *&MI)
> // TODO: Check for extraneous machine operands.
> MI = MF.CreateMachineInstr(MCID, DebugLocation, /*NoImplicit=*/true);
> MI->setFlags(Flags);
> - if (Ty.isValid())
> - MI->setType(Ty);
> + if (Tys.size() > 0) {
> + for (unsigned i = 0; i < Tys.size(); ++i)
> + MI->setType(Tys[i], i);
> + }
> for (const auto &Operand : Operands)
> MI->addOperand(MF, Operand.Operand);
> if (assignRegisterTies(*MI, Operands))
>
> Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Fri Jul 22 17:13:36 2016
> @@ -566,8 +566,13 @@ void MIPrinter::print(const MachineInstr
> OS << TII->getName(MI.getOpcode());
> if (isPreISelGenericOpcode(MI.getOpcode())) {
> assert(MI.getType().isValid() && "Generic instructions must have a type");
> - OS << ' ';
> - MI.getType().print(OS);
> + OS << " { ";
> + for (unsigned i = 0; i < MI.getNumTypes(); ++i) {
> + MI.getType().print(OS);
> + if (i + 1 != MI.getNumTypes())
> + OS << ", ";
> + }
> + OS << " } ";
> }
> if (I < E)
> OS << ' ';
>
> Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Jul 22 17:13:36 2016
> @@ -656,7 +656,7 @@ MachineInstr::MachineInstr(MachineFuncti
> debugLoc(std::move(dl))
> #ifdef LLVM_BUILD_GLOBAL_ISEL
> ,
> - Ty(LLT{})
> + Tys(0)
> #endif
> {
> assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
> @@ -680,7 +680,7 @@ MachineInstr::MachineInstr(MachineFuncti
> MemRefs(MI.MemRefs), debugLoc(MI.getDebugLoc())
> #ifdef LLVM_BUILD_GLOBAL_ISEL
> ,
> - Ty(LLT{})
> + Tys(0)
> #endif
> {
> assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
> @@ -710,18 +710,24 @@ MachineRegisterInfo *MachineInstr::getRe
> // The proper implementation is WIP and is tracked here:
> // PR26576.
> #ifndef LLVM_BUILD_GLOBAL_ISEL
> -void MachineInstr::setType(LLT Ty) {}
> +unsigned MachineInstr::getNumTypes() const { return 0; }
>
> -LLT MachineInstr::getType() const { return LLT{}; }
> +void MachineInstr::setType(LLT Ty, unsigned Idx) {}
> +
> +LLT MachineInstr::getType(unsigned Idx) const { return LLT{}; }
>
> #else
> -void MachineInstr::setType(LLT Ty) {
> +unsigned MachineInstr::getNumTypes() const { return Tys.size(); }
> +
> +void MachineInstr::setType(LLT Ty, unsigned Idx) {
Shouldn’t we change the APIs to use const LLT& since it is probably not that cheap to copy it around anymore?
> assert((!Ty.isValid() || isPreISelGenericOpcode(getOpcode())) &&
> "Non generic instructions are not supposed to be typed");
> - this->Ty = Ty;
> + if (Tys.size() < Idx + 1)
> + Tys.resize(Idx+1);
> + Tys[Idx] = Ty;
> }
>
> -LLT MachineInstr::getType() const { return Ty; }
> +LLT MachineInstr::getType(unsigned Idx) const { return Tys[Idx]; }
> #endif // LLVM_BUILD_GLOBAL_ISEL
>
> /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
> @@ -1724,10 +1730,14 @@ void MachineInstr::print(raw_ostream &OS
> else
> OS << "UNKNOWN";
>
> - if (getType().isValid()) {
> - OS << ' ';
> - getType().print(OS);
> - OS << ' ';
> + if (getNumTypes() > 0) {
> + OS << " { ";
> + for (unsigned i = 0; i < getNumTypes(); ++i) {
> + getType(i).print(OS);
> + if (i + 1 != getNumTypes())
> + OS << ", ";
> + }
> + OS << " } ";
> }
>
> if (SkipOpers)
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Fri Jul 22 17:13:36 2016
> @@ -9,7 +9,7 @@ target triple = "aarch64-apple-ios"
> ; CHECK: name: addi64
> ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
> -; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD s64 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD { s64 } [[ARG1]], [[ARG2]]
Could we avoid the {} when there is only one type?
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> define i64 @addi64(i64 %arg1, i64 %arg2) {
> @@ -23,9 +23,9 @@ define i64 @addi64(i64 %arg1, i64 %arg2)
> ; CHECK-NEXT: - { id: 0, name: ptr1, offset: 0, size: 8, alignment: 8 }
> ; CHECK-NEXT: - { id: 1, name: ptr2, offset: 0, size: 8, alignment: 1 }
> ; CHECK-NEXT: - { id: 2, name: ptr3, offset: 0, size: 128, alignment: 8 }
> -; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 0
> -; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 1
> -; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 2
> +; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX { p0 } 0
> +; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX { p0 } 1
> +; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX { p0 } 2
> define void @allocai64() {
> %ptr1 = alloca i64
> %ptr2 = alloca i64, align 1
> @@ -44,7 +44,7 @@ define void @allocai64() {
> ; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]]({{0x[a-f0-9]+ / 0x[a-f0-9]+}} = 100.00%)
> ;
> ; Check that we emit the correct branch.
> -; CHECK: G_BR unsized %[[END]]
> +; CHECK: G_BR { unsized } %[[END]]
> ;
> ; Check that end contains the return instruction.
> ; CHECK: [[END]]:
> @@ -59,7 +59,7 @@ end:
> ; CHECK: name: ori64
> ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
> -; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR s64 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR { s64 } [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> define i64 @ori64(i64 %arg1, i64 %arg2) {
> @@ -70,7 +70,7 @@ define i64 @ori64(i64 %arg1, i64 %arg2)
> ; CHECK: name: ori32
> ; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
> -; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR s32 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR { s32 } [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> define i32 @ori32(i32 %arg1, i32 %arg2) {
> @@ -82,7 +82,7 @@ define i32 @ori32(i32 %arg1, i32 %arg2)
> ; CHECK: name: andi64
> ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
> -; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_AND s64 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_AND { s64 } [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> define i64 @andi64(i64 %arg1, i64 %arg2) {
> @@ -93,7 +93,7 @@ define i64 @andi64(i64 %arg1, i64 %arg2)
> ; CHECK: name: andi32
> ; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
> -; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_AND s32 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_AND { s32 } [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> define i32 @andi32(i32 %arg1, i32 %arg2) {
> @@ -105,7 +105,7 @@ define i32 @andi32(i32 %arg1, i32 %arg2)
> ; CHECK: name: subi64
> ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
> -; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_SUB s64 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_SUB { s64 } [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> define i64 @subi64(i64 %arg1, i64 %arg2) {
> @@ -116,7 +116,7 @@ define i64 @subi64(i64 %arg1, i64 %arg2)
> ; CHECK: name: subi32
> ; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
> -; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SUB s32 [[ARG1]], [[ARG2]]
> +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SUB { s32 } [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> define i32 @subi32(i32 %arg1, i32 %arg2) {
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Fri Jul 22 17:13:36 2016
> @@ -68,8 +68,8 @@ registers:
> body: |
> bb.0.entry:
> liveins: %x0
> - ; CHECK: %0(32) = G_ADD s32 %w0
> - %0(32) = G_ADD s32 %w0, %w0
> + ; CHECK: %0(32) = G_ADD { s32 } %w0
> + %0(32) = G_ADD { s32 } %w0, %w0
> ...
>
> ---
> @@ -85,8 +85,8 @@ registers:
> body: |
> bb.0.entry:
> liveins: %d0
> - ; CHECK: %0(64) = G_ADD <2 x s32> %d0
> - %0(64) = G_ADD <2 x s32> %d0, %d0
> + ; CHECK: %0(64) = G_ADD { <2 x s32> } %d0
> + %0(64) = G_ADD { <2 x s32> } %d0, %d0
> ...
>
> ---
> @@ -107,9 +107,9 @@ body: |
> liveins: %s0, %x0
> ; CHECK: %0(32) = COPY %s0
> ; CHECK-NEXT: %2(32) = COPY %0
> - ; CHECK-NEXT: %1(32) = G_ADD s32 %2, %w0
> + ; CHECK-NEXT: %1(32) = G_ADD { s32 } %2, %w0
> %0(32) = COPY %s0
> - %1(32) = G_ADD s32 %0, %w0
> + %1(32) = G_ADD { s32 } %0, %w0
> ...
>
> # Check that we repair the assignment for %0 differently for both uses.
> @@ -129,9 +129,9 @@ body: |
> ; CHECK: %0(32) = COPY %s0
> ; CHECK-NEXT: %2(32) = COPY %0
> ; CHECK-NEXT: %3(32) = COPY %0
> - ; CHECK-NEXT: %1(32) = G_ADD s32 %2, %3
> + ; CHECK-NEXT: %1(32) = G_ADD { s32 } %2, %3
> %0(32) = COPY %s0
> - %1(32) = G_ADD s32 %0, %0
> + %1(32) = G_ADD { s32 } %0, %0
> ...
>
> ---
> @@ -152,10 +152,10 @@ body: |
> bb.0.entry:
> liveins: %w0
> ; CHECK: %0(32) = COPY %w0
> - ; CHECK-NEXT: %2(32) = G_ADD s32 %0, %w0
> + ; CHECK-NEXT: %2(32) = G_ADD { s32 } %0, %w0
> ; CHECK-NEXT: %1(32) = COPY %2
> %0(32) = COPY %w0
> - %1(32) = G_ADD s32 %0, %w0
> + %1(32) = G_ADD { s32 } %0, %w0
> ...
>
> ---
> @@ -187,7 +187,7 @@ body: |
>
> bb.1.then:
> successors: %bb.2.end
> - %3(32) = G_ADD s32 %0, %0
> + %3(32) = G_ADD { s32 } %0, %0
>
> bb.2.end:
> %4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then
> @@ -211,9 +211,9 @@ body: |
> liveins: %w0, %s0
> ; CHECK: %0(32) = COPY %w0
> ; CHECK-NEXT: %2(32) = COPY %s0
> - ; CHECK-NEXT: %1(32) = G_ADD s32 %0, %2
> + ; CHECK-NEXT: %1(32) = G_ADD { s32 } %0, %2
> %0(32) = COPY %w0
> - %1(32) = G_ADD s32 %0, %s0
> + %1(32) = G_ADD { s32 } %0, %s0
> ...
>
> ---
> @@ -229,10 +229,10 @@ body: |
> bb.0.entry:
> liveins: %w0
> ; CHECK: %0(32) = COPY %w0
> - ; CHECK-NEXT: %1(32) = G_ADD s32 %0, %0
> + ; CHECK-NEXT: %1(32) = G_ADD { s32 } %0, %0
> ; CHECK-NEXT: %s0 = COPY %1
> %0(32) = COPY %w0
> - %s0 = G_ADD s32 %0, %0
> + %s0 = G_ADD { s32 } %0, %0
> ...
>
> ---
> @@ -271,13 +271,13 @@ body: |
> ; FAST-NEXT: %3(64) = COPY %0
> ; FAST-NEXT: %4(64) = COPY %1
> ; The mapping of G_OR is on FPR.
> - ; FAST-NEXT: %2(64) = G_OR <2 x s32> %3, %4
> + ; FAST-NEXT: %2(64) = G_OR { <2 x s32> } %3, %4
>
> ; Greedy mode remapped the instruction on the GPR bank.
> - ; GREEDY-NEXT: %2(64) = G_OR <2 x s32> %0, %1
> + ; GREEDY-NEXT: %2(64) = G_OR { <2 x s32> } %0, %1
> %0(64) = COPY %x0
> %1(64) = COPY %x1
> - %2(64) = G_OR <2 x s32> %0, %1
> + %2(64) = G_OR { <2 x s32> } %0, %1
> ...
>
> ---
> @@ -317,13 +317,13 @@ body: |
> ; FAST-NEXT: %3(64) = COPY %0
> ; FAST-NEXT: %4(64) = COPY %1
> ; The mapping of G_OR is on FPR.
> - ; FAST-NEXT: %2(64) = G_OR <2 x s32> %3, %4
> + ; FAST-NEXT: %2(64) = G_OR { <2 x s32> } %3, %4
>
> ; Greedy mode remapped the instruction on the GPR bank.
> - ; GREEDY-NEXT: %3(64) = G_OR <2 x s32> %0, %1
> + ; GREEDY-NEXT: %3(64) = G_OR { <2 x s32> } %0, %1
> ; We need to keep %2 into FPR because we do not know anything about it.
> ; GREEDY-NEXT: %2(64) = COPY %3
> %0(64) = COPY %x0
> %1(64) = COPY %x1
> - %2(64) = G_OR <2 x s32> %0, %1
> + %2(64) = G_OR { <2 x s32> } %0, %1
> ...
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir Fri Jul 22 17:13:36 2016
> @@ -21,14 +21,14 @@ body: |
> bb.0.entry:
> liveins: %q0, %q1, %q2, %q3
> ; CHECK-LABEL: name: test_vector_add
> - ; CHECK-DAG: [[LHS_LO:%.*]](128), [[LHS_HI:%.*]](128) = G_EXTRACT <2 x s64> %0, 0, 128
> - ; CHECK-DAG: [[RHS_LO:%.*]](128), [[RHS_HI:%.*]](128) = G_EXTRACT <2 x s64> %1, 0, 128
> - ; CHECK: [[RES_LO:%.*]](128) = G_ADD <2 x s64> [[LHS_LO]], [[RHS_LO]]
> - ; CHECK: [[RES_HI:%.*]](128) = G_ADD <2 x s64> [[LHS_HI]], [[RHS_HI]]
> - ; CHECK: %2(256) = G_SEQUENCE <4 x s64> [[RES_LO]], [[RES_HI]]
> + ; CHECK-DAG: [[LHS_LO:%.*]](128), [[LHS_HI:%.*]](128) = G_EXTRACT { <2 x s64> } %0, 0, 128
> + ; CHECK-DAG: [[RHS_LO:%.*]](128), [[RHS_HI:%.*]](128) = G_EXTRACT { <2 x s64> } %1, 0, 128
> + ; CHECK: [[RES_LO:%.*]](128) = G_ADD { <2 x s64> } [[LHS_LO]], [[RHS_LO]]
> + ; CHECK: [[RES_HI:%.*]](128) = G_ADD { <2 x s64> } [[LHS_HI]], [[RHS_HI]]
> + ; CHECK: %2(256) = G_SEQUENCE { <4 x s64> } [[RES_LO]], [[RES_HI]]
>
> - %0(256) = G_SEQUENCE <4 x s64> %q0, %q1
> - %1(256) = G_SEQUENCE <4 x s64> %q2, %q3
> - %2(256) = G_ADD <4 x s64> %0, %1
> - %q0, %q1 = G_EXTRACT <2 x s64> %2, 0, 128
> + %0(256) = G_SEQUENCE { <4 x s64> } %q0, %q1
> + %1(256) = G_SEQUENCE { <4 x s64> } %q2, %q3
> + %2(256) = G_ADD { <4 x s64> } %0, %1
> + %q0, %q1 = G_EXTRACT { <2 x s64> } %2, 0, 128
> ...
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll Fri Jul 22 17:13:36 2016
> @@ -5,7 +5,7 @@
>
> ; Tests for add.
> ; CHECK: name: addi32
> -; CHECK: G_ADD s32
> +; CHECK: G_ADD { s32 }
> define i32 @addi32(i32 %arg1, i32 %arg2) {
> %res = add i32 %arg1, %arg2
> ret i32 %res
>
> Modified: llvm/trunk/test/CodeGen/MIR/X86/generic-virtual-registers.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/generic-virtual-registers.mir?rev=276481&r1=276480&r2=276481&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/X86/generic-virtual-registers.mir (original)
> +++ llvm/trunk/test/CodeGen/MIR/X86/generic-virtual-registers.mir Fri Jul 22 17:13:36 2016
> @@ -33,16 +33,16 @@ registers:
> body: |
> bb.0.entry:
> liveins: %edi
> - ; CHECK: %0(32) = G_ADD s32 %edi
> - %0(32) = G_ADD s32 %edi, %edi
> - ; CHECK: %1(64) = G_ADD <2 x s32> %edi
> - %1(64) = G_ADD <2 x s32> %edi, %edi
> - ; CHECK: %2(64) = G_ADD s64 %edi
> - %2(64) = G_ADD s64 %edi, %edi
> + ; CHECK: %0(32) = G_ADD { s32 } %edi
> + %0(32) = G_ADD { s32 } %edi, %edi
> + ; CHECK: %1(64) = G_ADD { <2 x s32> } %edi
> + %1(64) = G_ADD { <2 x s32> } %edi, %edi
> + ; CHECK: %2(64) = G_ADD { s64 } %edi
> + %2(64) = G_ADD { s64 } %edi, %edi
> ; G_ADD is actually not a valid operand for structure type,
> ; but that is the only one we have for now for testing.
> - ; CHECK: %3(64) = G_ADD s64 %edi
> - %3(64) = G_ADD s64 %edi, %edi
> - ; CHECK: %4(48) = G_ADD s48 %edi
> - %4(48) = G_ADD s48 %edi, %edi
> + ; CHECK: %3(64) = G_ADD { s64 } %edi
> + %3(64) = G_ADD { s64 } %edi, %edi
> + ; CHECK: %4(48) = G_ADD { s48 } %edi
> + %4(48) = G_ADD { s48 } %edi, %edi
> ...
>
>
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