[PATCH] D22398: MIRParser: Allow register class specification on operand

[Quentin Colombet via llvm-commits]

qcolombet added inline comments.

================
Comment at: lib/CodeGen/MIRParser/MIParser.cpp:138
@@ -136,2 +137,3 @@
   bool parseRegisterFlag(unsigned &Flags);
+  bool parseRegisterClass(const TargetRegisterClass *&RC);
   bool parseSubRegisterIndex(unsigned &SubReg);
----------------
parserRegisterClassOrBank?

================
Comment at: lib/CodeGen/MIRParser/MIParser.cpp:851
@@ +850,3 @@
+  if (RCNameI == PFS.Names2RegClasses.end())
+    return error("expected a register class name");
+  RC = RCNameI->getValue();
----------------
We should look for register banks as well.

================
Comment at: lib/CodeGen/MIRParser/MIParser.cpp:1010
@@ +1009,3 @@
+      return error(Loc,
+                   "register class specification expects a virtual register");
+    case VRegInfo::NORMAL:
----------------
I believe we should have the same syntax for register bank.

================
Comment at: test/CodeGen/MIR/X86/register-operand-class.mir:12
@@ +11,3 @@
+# CHECK:   - { id: 2, class: gr32 }
+# CHECK:   - { id: 3, class: gr16 }
+name: f
----------------
We shouldn’t need to emit that part anymore, right?
Probably a follow-up patch, though.


Repository:
  rL LLVM

https://reviews.llvm.org/D22398