[llvm] r276344 - [AArch64][Inline-Asm] Return the 32-bit floating point register class

[Akira Hatanaka via llvm-commits]

Author: ahatanak
Date: Thu Jul 21 16:39:05 2016
New Revision: 276344

URL: http://llvm.org/viewvc/llvm-project?rev=276344&view=rev
Log:
[AArch64][Inline-Asm] Return the 32-bit floating point register class
when constraint "w" is used on a 32-bit operand.

This enables compiling the following code, which used to error out in
the backend:

void foo1(int a) {
  asm volatile ("sqxtn h0, %s0\n" : : "w"(a):);
}

Fixes PR28633.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=276344&r1=276343&r2=276344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Jul 21 16:39:05 2016
@@ -4703,7 +4703,7 @@ AArch64TargetLowering::getRegForInlineAs
         return std::make_pair(0U, &AArch64::GPR64commonRegClass);
       return std::make_pair(0U, &AArch64::GPR32commonRegClass);
     case 'w':
-      if (VT == MVT::f32)
+      if (VT.getSizeInBits() == 32)
         return std::make_pair(0U, &AArch64::FPR32RegClass);
       if (VT.getSizeInBits() == 64)
         return std::make_pair(0U, &AArch64::FPR64RegClass);

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll?rev=276344&r1=276343&r2=276344&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll Thu Jul 21 16:39:05 2016
@@ -246,3 +246,11 @@ define <4 x float> @test_vreg_128bit(<4
   ; CHECK fadd v14.4s, v0.4s, v0.4s:
   ret <4 x float> %1
 }
+
+define void @test_constraint_w(i32 %a) {
+  ; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}}
+  ; CHECK: sqxtn h0, [[SREG]]
+
+  tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a)
+  ret void
+}