[PATCH] D21808: [WebAssembly] Handle debug information and virtual registers without crashing

[Derek Schuff via llvm-commits]

dschuff added a comment.

@aprantl
Yes, that's correct. (well, it's not an SSA-based representation but it does have the infinite register file). Backends are expected by various target-independent lowering code to have a few particular physical registers (primarily SP/FP), but after lowering to MachineInstr we actually replace those with virtual registers too and use vregs through all the common backend passes. Right before we emit, we actually do a re-numbering and coloring step (to try to reduce the total number of registers and map them into a 0-indexed number space).

Codegen-wise it's gone pretty smoothly; I did some refactoring on PrologEpilogInserter a couple months ago (which reminds me, I still owe a cleanup on that) but most of the passes do just fine. We will need some more work though for dealing with debug info and MC.


https://reviews.llvm.org/D21808