[llvm] r276293 - [AArch64] Load/store opt: Don't count transient instructions towards search limits.
Geoff Berry via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 21 08:20:25 PDT 2016
Author: gberry
Date: Thu Jul 21 10:20:25 2016
New Revision: 276293
URL: http://llvm.org/viewvc/llvm-project?rev=276293&view=rev
Log:
[AArch64] Load/store opt: Don't count transient instructions towards search limits.
Summary:
This change also changes findMatchingInsn and
findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account
when tracking register defs and uses, which could potentially inhibit
these optimizations in the presence of debug information.
Reviewers: mcrosier
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D22582
Added:
llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
Modified:
llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=276293&r1=276292&r2=276293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Thu Jul 21 10:20:25 2016
@@ -1114,8 +1114,9 @@ bool AArch64LoadStoreOpt::findMatchingSt
--MBBI;
MachineInstr &MI = *MBBI;
- // Don't count DBG_VALUE instructions towards the search limit.
- if (!MI.isDebugValue())
+ // Don't count transient instructions towards the search limit since there
+ // may be different numbers of them if e.g. debug information is present.
+ if (!MI.isTransient())
++Count;
// If the load instruction reads directly from the address to which the
@@ -1225,13 +1226,11 @@ AArch64LoadStoreOpt::findMatchingInsn(Ma
for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
MachineInstr &MI = *MBBI;
- // Skip DBG_VALUE instructions. Otherwise debug info can affect the
- // optimization by changing how far we scan.
- if (MI.isDebugValue())
- continue;
- // Now that we know this is a real instruction, count it.
- ++Count;
+ // Don't count transient instructions towards the search limit since there
+ // may be different numbers of them if e.g. debug information is present.
+ if (!MI.isTransient())
+ ++Count;
Flags.setSExtIdx(-1);
if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&
@@ -1498,12 +1497,11 @@ MachineBasicBlock::iterator AArch64LoadS
++MBBI;
for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
MachineInstr &MI = *MBBI;
- // Skip DBG_VALUE instructions.
- if (MI.isDebugValue())
- continue;
- // Now that we know this is a real instruction, count it.
- ++Count;
+ // Don't count transient instructions towards the search limit since there
+ // may be different numbers of them if e.g. debug information is present.
+ if (!MI.isTransient())
+ ++Count;
// If we found a match, return it.
if (isMatchingUpdateInsn(*I, MI, BaseReg, UnscaledOffset))
@@ -1552,8 +1550,9 @@ MachineBasicBlock::iterator AArch64LoadS
--MBBI;
MachineInstr &MI = *MBBI;
- // Don't count DBG_VALUE instructions towards the search limit.
- if (!MI.isDebugValue())
+ // Don't count transient instructions towards the search limit since there
+ // may be different numbers of them if e.g. debug information is present.
+ if (!MI.isTransient())
++Count;
// If we found a match, return it.
Added: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=276293&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir Thu Jul 21 10:20:25 2016
@@ -0,0 +1,141 @@
+# RUN: llc -run-pass=aarch64-ldst-opt %s -o - 2>&1 | FileCheck %s
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64--linux-gnu"
+
+ ; Function Attrs: nounwind
+ define i16 @promote-load-from-store(i32* %dst, i32 %x) #0 {
+ store i32 %x, i32* %dst
+ %dst16 = bitcast i32* %dst to i16*
+ %dst1 = getelementptr inbounds i16, i16* %dst16, i32 1
+ %x16 = load i16, i16* %dst1
+ ret i16 %x16
+ }
+
+ ; Function Attrs: nounwind
+ define void @store-pair(i32* %dst, i32 %x, i32 %y) #0 {
+ %dst01 = bitcast i32* %dst to i32*
+ %dst1 = getelementptr inbounds i32, i32* %dst, i32 1
+ store i32 %x, i32* %dst01
+ store i32 %x, i32* %dst1
+ ret void
+ }
+
+ attributes #0 = { nounwind }
+
+...
+---
+name: promote-load-from-store
+alignment: 2
+exposesReturnsTwice: false
+hasInlineAsm: false
+allVRegsAllocated: true
+isSSA: false
+tracksRegLiveness: false
+tracksSubRegLiveness: false
+liveins:
+ - { reg: '%x0' }
+ - { reg: '%w1' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+body: |
+ bb.0 (%ir-block.0):
+ liveins: %w1, %x0
+
+ STRWui killed %w1, %x0, 0 :: (store 4 into %ir.dst)
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ %w0 = LDRHHui killed %x0, 1 :: (load 2 from %ir.dst1)
+ RET %lr, implicit %w0
+
+...
+# CHECK-LABEL: name: promote-load-from-store
+# CHECK: STRWui killed %w1
+# CHECK: UBFMWri %w1
+---
+name: store-pair
+alignment: 2
+exposesReturnsTwice: false
+hasInlineAsm: false
+allVRegsAllocated: true
+isSSA: false
+tracksRegLiveness: false
+tracksSubRegLiveness: false
+liveins:
+ - { reg: '%x0' }
+ - { reg: '%w1' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+body: |
+ bb.0 (%ir-block.0):
+ liveins: %w1, %x0
+
+ STRWui %w1, %x0, 0 :: (store 4 into %ir.dst01)
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ CFI_INSTRUCTION 0
+ STRWui killed %w1, killed %x0, 1 :: (store 4 into %ir.dst1)
+ RET %lr
+
+...
+# CHECK-LABEL: name: store-pair
+# CHECK: STPWi
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