[llvm] r275636 - [lanai] Small cleanup: remove/comment out unused args
Jacques Pienaar via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 15 15:38:33 PDT 2016
Author: jpienaar
Date: Fri Jul 15 17:38:32 2016
New Revision: 275636
URL: http://llvm.org/viewvc/llvm-project?rev=275636&view=rev
Log:
[lanai] Small cleanup: remove/comment out unused args
Modified:
llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
llvm/trunk/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
llvm/trunk/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp
llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpp
llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.cpp
llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.h
llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp
llvm/trunk/lib/Target/Lanai/LanaiMCInstLower.h
llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp
llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
llvm/trunk/lib/Target/Lanai/LanaiSubtarget.cpp
llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.cpp
llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h
llvm/trunk/lib/Target/Lanai/LanaiTargetObjectFile.cpp
llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h
llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
Modified: llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp Fri Jul 15 17:38:32 2016
@@ -627,7 +627,7 @@ public:
}
};
-bool LanaiAsmParser::ParseDirective(AsmToken DirectiveId) { return true; }
+bool LanaiAsmParser::ParseDirective(AsmToken /*DirectiveId*/) { return true; }
bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
OperandVector &Operands,
@@ -640,6 +640,7 @@ bool LanaiAsmParser::MatchAndEmitInstruc
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
case Match_Success:
Out.EmitInstruction(Inst, SubtargetInfo);
+ Opcode = Inst.getOpcode();
return false;
case Match_MissingFeature:
return Error(IdLoc, "Instruction use requires option to be enabled");
@@ -688,10 +689,13 @@ std::unique_ptr<LanaiOperand> LanaiAsmPa
bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc,
SMLoc &EndLoc) {
+ const AsmToken &Tok = getParser().getTok();
+ StartLoc = Tok.getLoc();
+ EndLoc = Tok.getEndLoc();
std::unique_ptr<LanaiOperand> Op = parseRegister();
- if (Op != 0)
+ if (Op != nullptr)
RegNum = Op->getReg();
- return (Op == 0);
+ return (Op == nullptr);
}
std::unique_ptr<LanaiOperand> LanaiAsmParser::parseIdentifier() {
@@ -1133,7 +1137,7 @@ static bool MaybePredicatedInst(const Op
.Default(false);
}
-bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo & /*Info*/,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// First operand is token for instruction
Modified: llvm/trunk/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp Fri Jul 15 17:38:32 2016
@@ -30,7 +30,7 @@ namespace llvm {
extern Target TheLanaiTarget;
}
-static MCDisassembler *createLanaiDisassembler(const Target &T,
+static MCDisassembler *createLanaiDisassembler(const Target & /*T*/,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new LanaiDisassembler(STI, Ctx);
@@ -71,8 +71,8 @@ static DecodeStatus decodeShiftImm(MCIns
#include "LanaiGenDisassemblerTables.inc"
-static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
- uint64_t &Size, uint32_t &Insn) {
+static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t &Size,
+ uint32_t &Insn) {
// We want to read exactly 4 bytes of data.
if (Bytes.size() < 4) {
Size = 0;
@@ -127,14 +127,12 @@ static void PostOperandDecodeAdjust(MCIn
}
}
-DecodeStatus LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
- ArrayRef<uint8_t> Bytes,
- uint64_t Address,
- raw_ostream &VStream,
- raw_ostream &CStream) const {
+DecodeStatus LanaiDisassembler::getInstruction(
+ MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
+ raw_ostream & /*VStream*/, raw_ostream & /*CStream*/) const {
uint32_t Insn;
- DecodeStatus Result = readInstruction32(Bytes, Address, Size, Insn);
+ DecodeStatus Result = readInstruction32(Bytes, Size, Insn);
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
@@ -161,7 +159,8 @@ static const unsigned GPRDecoderTable[]
Lanai::R30, Lanai::R31};
DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address, const void *Decoder) {
+ uint64_t /*Address*/,
+ const void * /*Decoder*/) {
if (RegNo > 31)
return MCDisassembler::Fail;
Modified: llvm/trunk/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp Fri Jul 15 17:38:32 2016
@@ -137,7 +137,7 @@ bool LanaiInstPrinter::printAlias(const
void LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annotation,
- const MCSubtargetInfo &STI) {
+ const MCSubtargetInfo & /*STI*/) {
if (!printAlias(MI, OS) && !printAliasInstr(MI, OS))
printInstruction(MI, OS);
printAnnotation(OS, Annotation);
@@ -233,7 +233,7 @@ static void printMemoryImmediateOffset(c
void LanaiInstPrinter::printMemRiOperand(const MCInst *MI, int OpNo,
raw_ostream &OS,
- const char *Modifier) {
+ const char * /*Modifier*/) {
const MCOperand &RegOp = MI->getOperand(OpNo);
const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
const MCOperand &AluOp = MI->getOperand(OpNo + 2);
@@ -248,7 +248,7 @@ void LanaiInstPrinter::printMemRiOperand
void LanaiInstPrinter::printMemRrOperand(const MCInst *MI, int OpNo,
raw_ostream &OS,
- const char *Modifier) {
+ const char * /*Modifier*/) {
const MCOperand &RegOp = MI->getOperand(OpNo);
const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
const MCOperand &AluOp = MI->getOperand(OpNo + 2);
@@ -269,7 +269,7 @@ void LanaiInstPrinter::printMemRrOperand
void LanaiInstPrinter::printMemSplsOperand(const MCInst *MI, int OpNo,
raw_ostream &OS,
- const char *Modifier) {
+ const char * /*Modifier*/) {
const MCOperand &RegOp = MI->getOperand(OpNo);
const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
const MCOperand &AluOp = MI->getOperand(OpNo + 2);
Modified: llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpp Fri Jul 15 17:38:32 2016
@@ -47,8 +47,7 @@ public:
const char *getPassName() const override { return "Lanai Assembly Printer"; }
- void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
- const char *Modifier = 0);
+ void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override;
@@ -63,7 +62,7 @@ private:
} // end of anonymous namespace
void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O, const char *Modifier) {
+ raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
@@ -110,7 +109,7 @@ void LanaiAsmPrinter::printOperand(const
// PrintAsmOperand - Print out an operand for an inline asm expression.
bool LanaiAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant,
+ unsigned /*AsmVariant*/,
const char *ExtraCode, raw_ostream &O) {
// Does this asm operand have a single letter operand modifier?
if (ExtraCode && ExtraCode[0]) {
Modified: llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp Fri Jul 15 17:38:32 2016
@@ -83,7 +83,7 @@ char Filler::ID = 0;
// createLanaiDelaySlotFillerPass - Returns a pass that fills in delay
// slots in Lanai MachineFunctions
FunctionPass *
-llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine &tm) {
+llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine & /*tm*/) {
return new Filler();
}
Modified: llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.cpp Fri Jul 15 17:38:32 2016
@@ -140,7 +140,7 @@ void LanaiFrameLowering::emitPrologue(Ma
}
MachineBasicBlock::iterator LanaiFrameLowering::eliminateCallFramePseudoInstr(
- MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineFunction & /*MF*/, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
// Discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
return MBB.erase(I);
@@ -176,7 +176,7 @@ MachineBasicBlock::iterator LanaiFrameLo
// ld -8[%fp],%fp # restore the caller's frame pointer
// before RET and the delay slot filler will move RET such that these
// instructions execute in the delay slots of the load to PC.
-void LanaiFrameLowering::emitEpilogue(MachineFunction &MF,
+void LanaiFrameLowering::emitEpilogue(MachineFunction & /*MF*/,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
const LanaiInstrInfo &LII =
Modified: llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.h?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiFrameLowering.h Fri Jul 15 17:38:32 2016
@@ -46,7 +46,7 @@ public:
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
- bool hasFP(const MachineFunction &MF) const override { return true; }
+ bool hasFP(const MachineFunction & /*MF*/) const override { return true; }
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS = nullptr) const override;
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp Fri Jul 15 17:38:32 2016
@@ -201,7 +201,7 @@ bool LanaiDAGToDAGISel::selectAddrRiSpls
bool LanaiDAGToDAGISel::selectAddrRi(SDValue Addr, SDValue &Base,
SDValue &Offset, SDValue &AluOp) {
- return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RImode=*/true);
+ return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/true);
}
bool LanaiDAGToDAGISel::selectAddrSpls(SDValue Addr, SDValue &Base,
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp Fri Jul 15 17:38:32 2016
@@ -197,8 +197,8 @@ SDValue LanaiTargetLowering::LowerOperat
// Lanai Inline Assembly Support
//===----------------------------------------------------------------------===//
-unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT VT,
- SelectionDAG &DAG) const {
+unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
+ SelectionDAG & /*DAG*/) const {
// Only unallocatable registers should be matched here.
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("pc", Lanai::PC)
@@ -579,7 +579,7 @@ LanaiTargetLowering::LowerReturn(SDValue
// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
SDValue LanaiTargetLowering::LowerCCCCallTo(
SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
- bool IsTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
+ bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
@@ -626,7 +626,7 @@ SDValue LanaiTargetLowering::LowerCCCCal
Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
/*IsVolatile=*/false,
/*AlwaysInline=*/false,
- /*IsTailCall=*/false, MachinePointerInfo(),
+ /*isTailCall=*/false, MachinePointerInfo(),
MachinePointerInfo());
ByValArgs.push_back(FIPtr);
}
@@ -786,8 +786,7 @@ SDValue LanaiTargetLowering::LowerCallRe
//===----------------------------------------------------------------------===//
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
- SDValue &LHS, SDValue &RHS,
- SelectionDAG &DAG) {
+ SDValue &RHS, SelectionDAG &DAG) {
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
// For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
@@ -859,7 +858,7 @@ SDValue LanaiTargetLowering::LowerBR_CC(
SDValue Dest = Op.getOperand(4);
SDLoc DL(Op);
- LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
+ LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Flag =
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
@@ -961,7 +960,7 @@ SDValue LanaiTargetLowering::LowerSETCCE
SDValue Cond = Op.getOperand(3);
SDLoc DL(Op);
- LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
+ LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
@@ -973,7 +972,7 @@ SDValue LanaiTargetLowering::LowerSETCC(
SDValue Cond = Op.getOperand(2);
SDLoc DL(Op);
- LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
+ LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Flag =
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
@@ -990,7 +989,7 @@ SDValue LanaiTargetLowering::LowerSELECT
SDValue Cond = Op.getOperand(4);
SDLoc DL(Op);
- LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
+ LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Flag =
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
Modified: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp Fri Jul 15 17:38:32 2016
@@ -51,7 +51,7 @@ void LanaiInstrInfo::storeRegToStackSlot
MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
unsigned SourceRegister, bool IsKill, int FrameIndex,
const TargetRegisterClass *RegisterClass,
- const TargetRegisterInfo *RegisterInfo) const {
+ const TargetRegisterInfo * /*RegisterInfo*/) const {
DebugLoc DL;
if (Position != MBB.end()) {
DL = Position->getDebugLoc();
@@ -71,7 +71,7 @@ void LanaiInstrInfo::loadRegFromStackSlo
MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
unsigned DestinationRegister, int FrameIndex,
const TargetRegisterClass *RegisterClass,
- const TargetRegisterInfo *RegisterInfo) const {
+ const TargetRegisterInfo * /*RegisterInfo*/) const {
DebugLoc DL;
if (Position != MBB.end()) {
DL = Position->getDebugLoc();
@@ -86,9 +86,8 @@ void LanaiInstrInfo::loadRegFromStackSlo
.addImm(LPAC::ADD);
}
-bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa,
- MachineInstr &MIb,
- AliasAnalysis *AA) const {
+bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
+ MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis * /*AA*/) const {
assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
@@ -118,7 +117,7 @@ bool LanaiInstrInfo::areMemAccessesTrivi
return false;
}
-bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
+bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr & /*MI*/) const {
return false;
}
@@ -283,7 +282,7 @@ inline static unsigned flagSettingOpcode
}
bool LanaiInstrInfo::optimizeCompareInstr(
- MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
+ MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/,
int CmpValue, const MachineRegisterInfo *MRI) const {
// Get the unique definition of SrcReg.
MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
@@ -457,8 +456,7 @@ bool LanaiInstrInfo::analyzeSelect(const
// Identify instructions that can be folded into a SELECT instruction, and
// return the defining instruction.
static MachineInstr *canFoldIntoSelect(unsigned Reg,
- const MachineRegisterInfo &MRI,
- const TargetInstrInfo *TII) {
+ const MachineRegisterInfo &MRI) {
if (!TargetRegisterInfo::isVirtualRegister(Reg))
return nullptr;
if (!MRI.hasOneNonDBGUse(Reg))
@@ -495,13 +493,13 @@ static MachineInstr *canFoldIntoSelect(u
MachineInstr *
LanaiInstrInfo::optimizeSelect(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
- bool PreferFalse) const {
+ bool /*PreferFalse*/) const {
assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
- MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI, this);
+ MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
bool Invert = !DefMI;
if (!DefMI)
- DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI, this);
+ DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
if (!DefMI)
return nullptr;
@@ -552,7 +550,7 @@ LanaiInstrInfo::optimizeSelect(MachineIn
return NewMI;
}
-// The AnalyzeBranch function is used to examine conditional instructions and
+// The analyzeBranch function is used to examine conditional instructions and
// remove unnecessary instructions. This method is used by BranchFolder and
// IfConverter machine function passes to improve the CFG.
// - TrueBlock is set to the destination if condition evaluates true (it is the
@@ -749,7 +747,7 @@ unsigned LanaiInstrInfo::isStoreToStackS
bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(
MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo * /*TRI*/) const {
// Handle only loads/stores with base register followed by immediate offset
// and with add as ALU op.
if (LdSt.getNumOperands() != 4)
Modified: llvm/trunk/lib/Target/Lanai/LanaiMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiMCInstLower.h?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiMCInstLower.h Fri Jul 15 17:38:32 2016
@@ -31,7 +31,7 @@ class LLVM_LIBRARY_VISIBILITY LanaiMCIns
AsmPrinter &Printer;
public:
- LanaiMCInstLower(MCContext &CTX, Mangler &Mang, AsmPrinter &AP)
+ LanaiMCInstLower(MCContext &CTX, Mangler & /*Mang*/, AsmPrinter &AP)
: Ctx(CTX), Printer(AP) {}
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
Modified: llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiRegisterInfo.cpp Fri Jul 15 17:38:32 2016
@@ -34,7 +34,7 @@ using namespace llvm;
LanaiRegisterInfo::LanaiRegisterInfo() : LanaiGenRegisterInfo(Lanai::RCA) {}
const uint16_t *
-LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction * /*MF*/) const {
return CSR_SaveList;
}
@@ -61,12 +61,12 @@ BitVector LanaiRegisterInfo::getReserved
}
bool LanaiRegisterInfo::requiresRegisterScavenging(
- const MachineFunction &MF) const {
+ const MachineFunction & /*MF*/) const {
return true;
}
bool LanaiRegisterInfo::trackLivenessAfterRegAlloc(
- const MachineFunction &MF) const {
+ const MachineFunction & /*MF*/) const {
return true;
}
@@ -257,7 +257,8 @@ bool LanaiRegisterInfo::hasBasePointer(c
unsigned LanaiRegisterInfo::getRARegister() const { return Lanai::RCA; }
-unsigned LanaiRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+unsigned
+LanaiRegisterInfo::getFrameRegister(const MachineFunction & /*MF*/) const {
return Lanai::FP;
}
@@ -280,7 +281,7 @@ unsigned LanaiRegisterInfo::getEHHandler
}
const uint32_t *
-LanaiRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
- CallingConv::ID CC) const {
+LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
+ CallingConv::ID /*CC*/) const {
return CSR_RegMask;
}
Modified: llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp Fri Jul 15 17:38:32 2016
@@ -20,9 +20,11 @@
namespace llvm {
SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy(
- SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SelectionDAG & /*DAG*/, const SDLoc & /*dl*/, SDValue /*Chain*/,
+ SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, unsigned /*Align*/,
+ bool /*isVolatile*/, bool /*AlwaysInline*/,
+ MachinePointerInfo /*DstPtrInfo*/,
+ MachinePointerInfo /*SrcPtrInfo*/) const {
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
return SDValue();
Modified: llvm/trunk/lib/Target/Lanai/LanaiSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiSubtarget.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiSubtarget.cpp Fri Jul 15 17:38:32 2016
@@ -39,9 +39,9 @@ LanaiSubtarget &LanaiSubtarget::initiali
LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
StringRef FeatureString, const TargetMachine &TM,
- const TargetOptions &Options,
- CodeModel::Model CodeModel,
- CodeGenOpt::Level OptLevel)
+ const TargetOptions & /*Options*/,
+ CodeModel::Model /*CodeModel*/,
+ CodeGenOpt::Level /*OptLevel*/)
: LanaiGenSubtargetInfo(TargetTriple, Cpu, FeatureString),
FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
InstrInfo(), TLInfo(TM, *this), TSInfo() {}
Modified: llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.cpp Fri Jul 15 17:38:32 2016
@@ -35,7 +35,7 @@ extern "C" void LLVMInitializeLanaiTarge
RegisterTargetMachine<LanaiTargetMachine> registered_target(TheLanaiTarget);
}
-static std::string computeDataLayout(const Triple &TT) {
+static std::string computeDataLayout() {
// Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
return "E" // Big endian
"-m:e" // ELF name manging
@@ -46,8 +46,7 @@ static std::string computeDataLayout(con
"-S64"; // 64 bit natural stack alignment
}
-static Reloc::Model getEffectiveRelocModel(const Triple &TT,
- Optional<Reloc::Model> RM) {
+static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
if (!RM.hasValue())
return Reloc::PIC_;
return *RM;
@@ -59,9 +58,8 @@ LanaiTargetMachine::LanaiTargetMachine(c
Optional<Reloc::Model> RM,
CodeModel::Model CodeModel,
CodeGenOpt::Level OptLevel)
- : LLVMTargetMachine(T, computeDataLayout(TargetTriple), TT, Cpu,
- FeatureString, Options, getEffectiveRelocModel(TT, RM),
- CodeModel, OptLevel),
+ : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
+ getEffectiveRelocModel(RM), CodeModel, OptLevel),
Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel),
TLOF(new LanaiTargetObjectFile()) {
initAsmInfo();
Modified: llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h Fri Jul 15 17:38:32 2016
@@ -37,7 +37,7 @@ public:
CodeModel::Model CodeModel, CodeGenOpt::Level OptLevel);
const LanaiSubtarget *
- getSubtargetImpl(const llvm::Function &Fn) const override {
+ getSubtargetImpl(const llvm::Function & /*Fn*/) const override {
return &Subtarget;
}
Modified: llvm/trunk/lib/Target/Lanai/LanaiTargetObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiTargetObjectFile.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiTargetObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiTargetObjectFile.cpp Fri Jul 15 17:38:32 2016
@@ -72,7 +72,7 @@ bool LanaiTargetObjectFile::isGlobalInSm
// section. This method does all the work, except for checking the section
// kind.
bool LanaiTargetObjectFile::isGlobalInSmallSectionImpl(
- const GlobalValue *GV, const TargetMachine &TM) const {
+ const GlobalValue *GV, const TargetMachine & /*TM*/) const {
// Only global variables, not functions.
const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
if (!GVA)
Modified: llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiTargetTransformInfo.h Fri Jul 15 17:38:32 2016
@@ -44,8 +44,7 @@ public:
LanaiTTIImpl(const LanaiTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
LanaiTTIImpl(LanaiTTIImpl &&Arg)
- : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
- TLI(std::move(Arg.TLI)) {}
+ : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(Arg.ST), TLI(Arg.TLI) {}
bool shouldBuildLookupTables() const { return false; }
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp Fri Jul 15 17:38:32 2016
@@ -55,9 +55,9 @@ public:
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
// No instruction requires relaxation
- bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
- const MCRelaxableFragment *DF,
- const MCAsmLayout &Layout) const override {
+ bool fixupNeedsRelaxation(const MCFixup & /*Fixup*/, uint64_t /*Value*/,
+ const MCRelaxableFragment * /*DF*/,
+ const MCAsmLayout & /*Layout*/) const override {
return false;
}
@@ -67,10 +67,13 @@ public:
return Lanai::NumTargetFixupKinds;
}
- bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
+ bool mayNeedRelaxation(const MCInst & /*Inst*/) const override {
+ return false;
+ }
- void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
- MCInst &Res) const override {}
+ void relaxInstruction(const MCInst & /*Inst*/,
+ const MCSubtargetInfo & /*STI*/,
+ MCInst & /*Res*/) const override {}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
};
@@ -86,8 +89,8 @@ bool LanaiAsmBackend::writeNopData(uint6
}
void LanaiAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
- unsigned DataSize, uint64_t Value,
- bool IsPCRel) const {
+ unsigned /*DataSize*/, uint64_t Value,
+ bool /*IsPCRel*/) const {
MCFixupKind Kind = Fixup.getKind();
Value = adjustFixupValue(static_cast<unsigned>(Kind), Value);
@@ -159,9 +162,9 @@ LanaiAsmBackend::getFixupKindInfo(MCFixu
} // namespace
MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T,
- const MCRegisterInfo &MRI,
+ const MCRegisterInfo & /*MRI*/,
const Triple &TheTriple,
- StringRef CPU) {
+ StringRef /*CPU*/) {
if (!TheTriple.isOSBinFormatELF())
llvm_unreachable("OS not supported");
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp Fri Jul 15 17:38:32 2016
@@ -33,15 +33,15 @@ protected:
} // namespace
LanaiELFObjectWriter::LanaiELFObjectWriter(uint8_t OSABI)
- : MCELFObjectTargetWriter(/*Is64Bit=*/false, OSABI, ELF::EM_LANAI,
+ : MCELFObjectTargetWriter(/*Is64Bit_=*/false, OSABI, ELF::EM_LANAI,
/*HasRelocationAddend=*/true) {}
LanaiELFObjectWriter::~LanaiELFObjectWriter() {}
-unsigned LanaiELFObjectWriter::getRelocType(MCContext &Ctx,
- const MCValue &Target,
+unsigned LanaiELFObjectWriter::getRelocType(MCContext & /*Ctx*/,
+ const MCValue & /*Target*/,
const MCFixup &Fixup,
- bool IsPCRel) const {
+ bool /*IsPCRel*/) const {
unsigned Type;
unsigned Kind = static_cast<unsigned>(Fixup.getKind());
switch (Kind) {
@@ -74,7 +74,7 @@ unsigned LanaiELFObjectWriter::getRelocT
return Type;
}
-bool LanaiELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &SD,
+bool LanaiELFObjectWriter::needsRelocateWithSymbol(const MCSymbol & /*SD*/,
unsigned Type) const {
switch (Type) {
case ELF::R_LANAI_21:
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp Fri Jul 15 17:38:32 2016
@@ -19,7 +19,7 @@ using namespace llvm;
void LanaiMCAsmInfo::anchor() {}
-LanaiMCAsmInfo::LanaiMCAsmInfo(const Triple &TheTriple) {
+LanaiMCAsmInfo::LanaiMCAsmInfo(const Triple & /*TheTriple*/) {
IsLittleEndian = false;
PrivateGlobalPrefix = ".L";
WeakRefDirective = "\t.weak\t";
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp Fri Jul 15 17:38:32 2016
@@ -320,6 +320,7 @@ unsigned LanaiMCCodeEmitter::getBranchTa
llvm::MCCodeEmitter *
llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo,
- const MCRegisterInfo &MRI, MCContext &context) {
+ const MCRegisterInfo & /*MRI*/,
+ MCContext &context) {
return new LanaiMCCodeEmitter(InstrInfo, context);
}
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h Fri Jul 15 17:38:32 2016
@@ -45,7 +45,7 @@ public:
}
// There are no TLS LanaiMCExprs at the moment.
- void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
+ void fixELFSymbolsInTLSFixups(MCAssembler & /*Asm*/) const override {}
static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;
Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp?rev=275636&r1=275635&r2=275636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp Fri Jul 15 17:38:32 2016
@@ -39,7 +39,7 @@ static MCInstrInfo *createLanaiMCInstrIn
return X;
}
-static MCRegisterInfo *createLanaiMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createLanaiMCRegisterInfo(const Triple & /*TT*/) {
MCRegisterInfo *X = new MCRegisterInfo();
InitLanaiMCRegisterInfo(X, Lanai::RCA, 0, 0, Lanai::PC);
return X;
@@ -63,7 +63,7 @@ static MCStreamer *createMCStreamer(cons
return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
}
-static MCInstPrinter *createLanaiMCInstPrinter(const Triple &T,
+static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
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