[llvm] r275569 - [Hexagon] Improve patterns with stack-based addressing
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 15 08:35:53 PDT 2016
Author: kparzysz
Date: Fri Jul 15 10:35:52 2016
New Revision: 275569
URL: http://llvm.org/viewvc/llvm-project?rev=275569&view=rev
Log:
[Hexagon] Improve patterns with stack-based addressing
- Treat bitwise OR with a frame index as an ADD wherever possible, fold it
into addressing mode.
- Extend patterns for memops to allow memops with frame indexes as address
operands.
Added:
llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll
llvm/trunk/test/CodeGen/Hexagon/memops.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Fri Jul 15 10:35:52 2016
@@ -177,6 +177,7 @@ public:
private:
bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
+ bool orIsAdd(const SDNode *N) const;
bool isAlignedMemNode(const MemSDNode *N) const;
}; // end HexagonDAGToDAGISel
} // end anonymous namespace
@@ -1516,6 +1517,25 @@ bool HexagonDAGToDAGISel::isValueExtensi
}
return false;
}
+
+
+bool HexagonDAGToDAGISel::orIsAdd(const SDNode *N) const {
+ assert(N->getOpcode() == ISD::OR);
+ auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+ assert(C);
+
+ // Detect when "or" is used to add an offset to a stack object.
+ if (auto *FN = dyn_cast<FrameIndexSDNode>(N->getOperand(0))) {
+ MachineFrameInfo *MFI = MF->getFrameInfo();
+ unsigned A = MFI->getObjectAlignment(FN->getIndex());
+ assert(isPowerOf2_32(A));
+ int32_t Off = C->getSExtValue();
+ // If the alleged offset fits in the zero bits guaranteed by
+ // the alignment, then this or is really an add.
+ return (Off >= 0) && (((A-1) & Off) == unsigned(Off));
+ }
+ return false;
+}
bool HexagonDAGToDAGISel::isAlignedMemNode(const MemSDNode *N) const {
return N->getAlignment() >= N->getMemoryVT().getStoreSize();
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Jul 15 10:35:52 2016
@@ -2612,6 +2612,21 @@ bool HexagonInstrInfo::isValidOffset(uns
case Hexagon::J2_loop0i:
case Hexagon::J2_loop1i:
return isUInt<10>(Offset);
+
+ case Hexagon::S4_storeirb_io:
+ case Hexagon::S4_storeirbt_io:
+ case Hexagon::S4_storeirbf_io:
+ return isUInt<6>(Offset);
+
+ case Hexagon::S4_storeirh_io:
+ case Hexagon::S4_storeirht_io:
+ case Hexagon::S4_storeirhf_io:
+ return isShiftedUInt<6,1>(Offset);
+
+ case Hexagon::S4_storeiri_io:
+ case Hexagon::S4_storeirit_io:
+ case Hexagon::S4_storeirif_io:
+ return isShiftedUInt<6,2>(Offset);
}
if (Extend)
@@ -2687,9 +2702,6 @@ bool HexagonInstrInfo::isValidOffset(uns
case Hexagon::L2_ploadrubf_io:
case Hexagon::S2_pstorerbt_io:
case Hexagon::S2_pstorerbf_io:
- case Hexagon::S4_storeirb_io:
- case Hexagon::S4_storeirbt_io:
- case Hexagon::S4_storeirbf_io:
return isUInt<6>(Offset);
case Hexagon::L2_ploadrht_io:
@@ -2698,18 +2710,12 @@ bool HexagonInstrInfo::isValidOffset(uns
case Hexagon::L2_ploadruhf_io:
case Hexagon::S2_pstorerht_io:
case Hexagon::S2_pstorerhf_io:
- case Hexagon::S4_storeirh_io:
- case Hexagon::S4_storeirht_io:
- case Hexagon::S4_storeirhf_io:
return isShiftedUInt<6,1>(Offset);
case Hexagon::L2_ploadrit_io:
case Hexagon::L2_ploadrif_io:
case Hexagon::S2_pstorerit_io:
case Hexagon::S2_pstorerif_io:
- case Hexagon::S4_storeiri_io:
- case Hexagon::S4_storeirit_io:
- case Hexagon::S4_storeirif_io:
return isShiftedUInt<6,2>(Offset);
case Hexagon::L2_ploadrdt_io:
@@ -3066,8 +3072,6 @@ bool HexagonInstrInfo::getBaseAndOffsetP
unsigned &BasePos, unsigned &OffsetPos) const {
// Deal with memops first.
if (isMemOp(MI)) {
- assert (MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
- "Bad Memop.");
BasePos = 0;
OffsetPos = 1;
} else if (MI->mayStore()) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Fri Jul 15 10:35:52 2016
@@ -32,6 +32,9 @@ def LoReg: OutPatFrag<(ops node:$Rs),
def HiReg: OutPatFrag<(ops node:$Rs),
(EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
+def orisadd: PatFrag<(ops node:$Addr, node:$off),
+ (or node:$Addr, node:$off), [{ return orIsAdd(N); }]>;
+
// SDNode for converting immediate C to C-1.
def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
@@ -1787,6 +1790,8 @@ multiclass Loadx_pat<PatFrag Load, Value
def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
(VT (MI AddrFI:$fi, imm:$Off))>;
+ def: Pat<(VT (Load (orisadd (i32 AddrFI:$fi), ImmPred:$Off))),
+ (VT (MI AddrFI:$fi, imm:$Off))>;
def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
(VT (MI IntRegs:$Rs, imm:$Off))>;
def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
@@ -3540,14 +3545,20 @@ let addrMode = BaseImmOffset, InputType
// AddedComplexity) to the individual patterns.
class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
: Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
-class Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
- InstHexagon MI>
- : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
- (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
-class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
- InstHexagon MI>
- : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
- (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+multiclass Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+ InstHexagon MI> {
+ def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
+ (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
+ def: Pat<(Store Value:$Rs, (orisadd (i32 AddrFI:$fi), ImmPred:$Off)),
+ (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
+}
+multiclass Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+ InstHexagon MI> {
+ def: Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
+ (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+ def: Pat<(Store Value:$Rt, (orisadd (i32 IntRegs:$Rs), ImmPred:$Off)),
+ (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+}
class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
: Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
(MI IntRegs:$Rs, 0, Value:$Rt)>;
@@ -3559,14 +3570,20 @@ class Storexm_fi_pat<PatFrag Store, PatF
InstHexagon MI>
: Pat<(Store Value:$Rs, AddrFI:$fi),
(MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
-class Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
- PatFrag ValueMod, InstHexagon MI>
- : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
- (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
-class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
- PatFrag ValueMod, InstHexagon MI>
- : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
- (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
+multiclass Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+ PatFrag ValueMod, InstHexagon MI> {
+ def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
+ (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
+ def: Pat<(Store Value:$Rs, (orisadd (i32 AddrFI:$fi), ImmPred:$Off)),
+ (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
+}
+multiclass Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+ PatFrag ValueMod, InstHexagon MI> {
+ def: Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
+ (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
+ def: Pat<(Store Value:$Rt, (orisadd (i32 IntRegs:$Rs), ImmPred:$Off)),
+ (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
+}
class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
InstHexagon MI>
: Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
@@ -3574,16 +3591,16 @@ class Storexm_simple_pat<PatFrag Store,
multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
InstHexagon MI> {
- def: Storex_fi_pat <Store, Value, MI>;
- def: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
- def: Storex_add_pat <Store, Value, ImmPred, MI>;
+ def: Storex_fi_pat <Store, Value, MI>;
+ defm: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
+ defm: Storex_add_pat <Store, Value, ImmPred, MI>;
}
multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
PatFrag ValueMod, InstHexagon MI> {
- def: Storexm_fi_pat <Store, Value, ValueMod, MI>;
- def: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
- def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>;
+ def: Storexm_fi_pat <Store, Value, ValueMod, MI>;
+ defm: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
+ defm: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>;
}
// Regular stores in the DAG have two operands: value and address.
@@ -4503,6 +4520,9 @@ let isMoveImm = 1, isAsCheapAsAMove = 1,
(ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
}
+def: Pat<(i32 (orisadd (i32 AddrFI:$Rs), s32ImmPred:$off)),
+ (i32 (TFR_FI (i32 AddrFI:$Rs), s32ImmPred:$off))>;
+
//===----------------------------------------------------------------------===//
// CRUSER - Type.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Fri Jul 15 10:35:52 2016
@@ -1188,17 +1188,52 @@ def ToImmByte : OutPatFrag<(ops node:$R)
def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
+// Emit store-immediate, but only when the stored value will not be constant-
+// extended. The reason for that is that there is no pass that can optimize
+// constant extenders in store-immediate instructions. In some cases we can
+// end up will a number of such stores, all of which store the same extended
+// value (e.g. after unrolling a loop that initializes floating point array).
+
+// Predicates to determine if the 16-bit immediate is expressible as a sign-
+// extended 8-bit immediate. Store-immediate-halfword will ignore any bits
+// beyond 0..15, so we don't care what is in there.
+
+def i16in8ImmPred: PatLeaf<(i32 imm), [{
+ int64_t v = (int16_t)N->getSExtValue();
+ return v == (int64_t)(int8_t)v;
+}]>;
+
+// Predicates to determine if the 32-bit immediate is expressible as a sign-
+// extended 8-bit immediate.
+def i32in8ImmPred: PatLeaf<(i32 imm), [{
+ int64_t v = (int32_t)N->getSExtValue();
+ return v == (int64_t)(int8_t)v;
+}]>;
+
+
let AddedComplexity = 40 in {
- // Not using frameindex patterns for these stores, because the offset
- // is not extendable. This could cause problems during removing the frame
- // indices, since the offset with respect to R29/R30 may not fit in the
- // u6 field.
- def: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
- S4_storeirb_io>;
- def: Storexm_add_pat<truncstorei16, s32ImmPred, u6_1ImmPred, ToImmHalf,
- S4_storeirh_io>;
- def: Storexm_add_pat<store, s32ImmPred, u6_2ImmPred, ToImmWord,
- S4_storeiri_io>;
+ // Even though the offset is not extendable in the store-immediate, we
+ // can still generate the fi# in the base address. If the final offset
+ // is not valid for the instruction, we will replace it with a scratch
+ // register.
+// def: Storexm_fi_pat <truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
+// def: Storexm_fi_pat <truncstorei16, i16in8ImmPred, ToImmHalf,
+// S4_storeirh_io>;
+// def: Storexm_fi_pat <store, i32in8ImmPred, ToImmWord, S4_storeiri_io>;
+
+// defm: Storexm_fi_add_pat <truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
+// S4_storeirb_io>;
+// defm: Storexm_fi_add_pat <truncstorei16, i16in8ImmPred, u6_1ImmPred,
+// ToImmHalf, S4_storeirh_io>;
+// defm: Storexm_fi_add_pat <store, i32in8ImmPred, u6_2ImmPred, ToImmWord,
+// S4_storeiri_io>;
+
+ defm: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
+ S4_storeirb_io>;
+ defm: Storexm_add_pat<truncstorei16, i16in8ImmPred, u6_1ImmPred, ToImmHalf,
+ S4_storeirh_io>;
+ defm: Storexm_add_pat<store, i32in8ImmPred, u6_2ImmPred, ToImmWord,
+ S4_storeiri_io>;
}
def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
@@ -2783,79 +2818,75 @@ def S4_lsli: SInst <(outs IntRegs:$Rd),
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-// MEMOP: Word, Half, Byte
+// MEMOP
//===----------------------------------------------------------------------===//
-def MEMOPIMM : SDNodeXForm<imm, [{
- // Call the transformation function XformM5ToU5Imm to get the negative
- // immediate's positive counterpart.
- int32_t imm = N->getSExtValue();
- return XformM5ToU5Imm(imm, SDLoc(N));
+def m5Imm8Pred : PatLeaf<(i32 imm), [{
+ int32_t v = (int8_t)N->getSExtValue();
+ return v >= -32 && v <= -1;
}]>;
-def MEMOPIMM_HALF : SDNodeXForm<imm, [{
- // -1 .. -31 represented as 65535..65515
- // assigning to a short restores our desired signed value.
- // Call the transformation function XformM5ToU5Imm to get the negative
- // immediate's positive counterpart.
- int16_t imm = N->getSExtValue();
- return XformM5ToU5Imm(imm, SDLoc(N));
+def m5Imm16Pred : PatLeaf<(i32 imm), [{
+ int32_t v = (int16_t)N->getSExtValue();
+ return v >= -32 && v <= -1;
}]>;
-def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
- // -1 .. -31 represented as 255..235
- // assigning to a char restores our desired signed value.
- // Call the transformation function XformM5ToU5Imm to get the negative
- // immediate's positive counterpart.
- int8_t imm = N->getSExtValue();
- return XformM5ToU5Imm(imm, SDLoc(N));
+def Clr5Imm8Pred : PatLeaf<(i32 imm), [{
+ uint32_t v = (uint8_t)~N->getZExtValue();
+ return ImmIsSingleBit(v);
}]>;
-def SETMEMIMM : SDNodeXForm<imm, [{
- // Return the bit position we will set [0-31].
- // As an SDNode.
- int32_t imm = N->getSExtValue();
+def Clr5Imm16Pred : PatLeaf<(i32 imm), [{
+ uint32_t v = (uint16_t)~N->getZExtValue();
+ return ImmIsSingleBit(v);
+}]>;
+
+def Set5Imm8 : SDNodeXForm<imm, [{
+ uint32_t imm = (uint8_t)N->getZExtValue();
return XformMskToBitPosU5Imm(imm, SDLoc(N));
}]>;
-def CLRMEMIMM : SDNodeXForm<imm, [{
- // Return the bit position we will clear [0-31].
- // As an SDNode.
- // we bit negate the value first
- int32_t imm = ~(N->getSExtValue());
+def Set5Imm16 : SDNodeXForm<imm, [{
+ uint32_t imm = (uint16_t)N->getZExtValue();
return XformMskToBitPosU5Imm(imm, SDLoc(N));
}]>;
-def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
- // Return the bit position we will set [0-15].
- // As an SDNode.
- int16_t imm = N->getSExtValue();
- return XformMskToBitPosU4Imm(imm, SDLoc(N));
+def Set5Imm32 : SDNodeXForm<imm, [{
+ uint32_t imm = (uint32_t)N->getZExtValue();
+ return XformMskToBitPosU5Imm(imm, SDLoc(N));
}]>;
-def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
- // Return the bit position we will clear [0-15].
- // As an SDNode.
- // we bit negate the value first
- int16_t imm = ~(N->getSExtValue());
- return XformMskToBitPosU4Imm(imm, SDLoc(N));
+def Clr5Imm8 : SDNodeXForm<imm, [{
+ uint32_t imm = (uint8_t)~N->getZExtValue();
+ return XformMskToBitPosU5Imm(imm, SDLoc(N));
}]>;
-def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
- // Return the bit position we will set [0-7].
- // As an SDNode.
- int8_t imm = N->getSExtValue();
- return XformMskToBitPosU3Imm(imm, SDLoc(N));
+def Clr5Imm16 : SDNodeXForm<imm, [{
+ uint32_t imm = (uint16_t)~N->getZExtValue();
+ return XformMskToBitPosU5Imm(imm, SDLoc(N));
}]>;
-def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
- // Return the bit position we will clear [0-7].
- // As an SDNode.
- // we bit negate the value first
- int8_t imm = ~(N->getSExtValue());
- return XformMskToBitPosU3Imm(imm, SDLoc(N));
+def Clr5Imm32 : SDNodeXForm<imm, [{
+ int32_t imm = (int32_t)~N->getZExtValue();
+ return XformMskToBitPosU5Imm(imm, SDLoc(N));
}]>;
+def NegImm8 : SDNodeXForm<imm, [{
+ int8_t V = N->getSExtValue();
+ return CurDAG->getTargetConstant(-V, SDLoc(N), MVT::i32);
+}]>;
+
+def NegImm16 : SDNodeXForm<imm, [{
+ int16_t V = N->getSExtValue();
+ return CurDAG->getTargetConstant(-V, SDLoc(N), MVT::i32);
+}]>;
+
+def NegImm32 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
+}]>;
+
+def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>;
+
//===----------------------------------------------------------------------===//
// Template class for MemOp instructions with the register value.
//===----------------------------------------------------------------------===//
@@ -2952,197 +2983,234 @@ let isExtendable = 1, opExtendable = 1,
defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
}
-//===----------------------------------------------------------------------===//
-// Multiclass to define 'Def Pats' for ALU operations on the memory
-// Here value used for the ALU operation is an immediate value.
-// mem[bh](Rs+#0) += #U5
-// mem[bh](Rs+#u6) += #U5
-//===----------------------------------------------------------------------===//
-
-multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
- InstHexagon MI, SDNode OpNode> {
- let AddedComplexity = 180 in
- def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
- IntRegs:$addr),
- (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
-
- let AddedComplexity = 190 in
- def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
- u5ImmPred:$addend),
- (add IntRegs:$base, ImmPred:$offset)),
- (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
-}
-
-multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
- InstHexagon addMI, InstHexagon subMI> {
- defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, addMI, add>;
- defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, subMI, sub>;
-}
-
-multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
- // Half Word
- defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
- L4_iadd_memoph_io, L4_isub_memoph_io>;
- // Byte
- defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u32ImmPred,
- L4_iadd_memopb_io, L4_isub_memopb_io>;
-}
-
-let Predicates = [UseMEMOP] in {
- defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
- defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
- defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
-
- // Word
- defm: MemOpi_u5ALUOp <load, store, u30_2ImmPred, L4_iadd_memopw_io,
- L4_isub_memopw_io>;
-}
-
-//===----------------------------------------------------------------------===//
-// multiclass to define 'Def Pats' for ALU operations on the memory.
-// Here value used for the ALU operation is a negative value.
-// mem[bh](Rs+#0) += #m5
-// mem[bh](Rs+#u6) += #m5
-//===----------------------------------------------------------------------===//
-
-multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
- PatLeaf immPred, SDNodeXForm xformFunc,
- InstHexagon MI> {
- let AddedComplexity = 190 in
- def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
- (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
-
- let AddedComplexity = 195 in
- def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
- immPred:$subend),
- (add IntRegs:$base, ImmPred:$offset)),
- (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
-}
-
-multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
- // Half Word
- defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u31_1ImmPred, m5HImmPred,
- MEMOPIMM_HALF, L4_isub_memoph_io>;
- // Byte
- defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u32ImmPred, m5BImmPred,
- MEMOPIMM_BYTE, L4_isub_memopb_io>;
-}
-
-let Predicates = [UseMEMOP] in {
- defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
- defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
- defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
-
- // Word
- defm: MemOpi_m5Pats <load, store, u30_2ImmPred, m5ImmPred,
- MEMOPIMM, L4_isub_memopw_io>;
-}
-
-//===----------------------------------------------------------------------===//
-// Multiclass to define 'def Pats' for bit operations on the memory.
-// mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
-// mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
-//===----------------------------------------------------------------------===//
-
-multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
- PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
- SDNode OpNode> {
-
- // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
- let AddedComplexity = 250 in
- def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
- immPred:$bitend),
- (add IntRegs:$base, extPred:$offset)),
- (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
-
- // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
- let AddedComplexity = 225 in
- def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
- (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
-}
-
-multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
- // Byte - clrbit
- defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u32ImmPred,
- CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
- // Byte - setbit
- defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u32ImmPred,
- SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
- // Half Word - clrbit
- defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u31_1ImmPred,
- CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
- // Half Word - setbit
- defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u31_1ImmPred,
- SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
-}
-
-let Predicates = [UseMEMOP] in {
- // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
- // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
- defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
- defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
- defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
-
- // memw(Rs+#0) = [clrbit|setbit](#U5)
- // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
- defm: MemOpi_bitPats<load, store, Clr5ImmPred, u30_2ImmPred, CLRMEMIMM,
- L4_iand_memopw_io, and>;
- defm: MemOpi_bitPats<load, store, Set5ImmPred, u30_2ImmPred, SETMEMIMM,
- L4_ior_memopw_io, or>;
-}
-
-//===----------------------------------------------------------------------===//
-// Multiclass to define 'def Pats' for ALU operations on the memory
-// where addend is a register.
-// mem[bhw](Rs+#0) [+-&|]= Rt
-// mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
-//===----------------------------------------------------------------------===//
-
-multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
- InstHexagon MI, SDNode OpNode> {
- let AddedComplexity = 141 in
- // mem[bhw](Rs+#0) [+-&|]= Rt
- def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
- IntRegs:$addr),
- (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
-
- // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
- let AddedComplexity = 150 in
- def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
- (i32 IntRegs:$orend)),
- (add IntRegs:$base, extPred:$offset)),
- (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
-}
-
-multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
- InstHexagon addMI, InstHexagon subMI,
- InstHexagon andMI, InstHexagon orMI> {
- defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
- defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
- defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
- defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
-}
-
-multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
- // Half Word
- defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
- L4_add_memoph_io, L4_sub_memoph_io,
- L4_and_memoph_io, L4_or_memoph_io>;
- // Byte
- defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u32ImmPred,
- L4_add_memopb_io, L4_sub_memopb_io,
- L4_and_memopb_io, L4_or_memopb_io>;
-}
-
-// Define 'def Pats' for MemOps with register addend.
-let Predicates = [UseMEMOP] in {
- // Byte, Half Word
- defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
- defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
- defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
- // Word
- defm: MemOPr_ALUOp <load, store, u30_2ImmPred, L4_add_memopw_io,
- L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
+
+multiclass Memopxr_simple_pat<PatFrag Load, PatFrag Store, SDNode Oper,
+ InstHexagon MI> {
+ // Addr: i32
+ def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs),
+ (MI I32:$Rs, 0, I32:$A)>;
+ // Addr: fi
+ def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs),
+ (MI AddrFI:$Rs, 0, I32:$A)>;
+}
+
+multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
+ SDNode Oper, InstHexagon MI> {
+ // Addr: i32
+ def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A),
+ (add I32:$Rs, ImmPred:$Off)),
+ (MI I32:$Rs, imm:$Off, I32:$A)>;
+ def: Pat<(Store (Oper (Load (orisadd I32:$Rs, ImmPred:$Off)), I32:$A),
+ (orisadd I32:$Rs, ImmPred:$Off)),
+ (MI I32:$Rs, imm:$Off, I32:$A)>;
+ // Addr: fi
+ def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A),
+ (add AddrFI:$Rs, ImmPred:$Off)),
+ (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
+ def: Pat<(Store (Oper (Load (orisadd AddrFI:$Rs, ImmPred:$Off)), I32:$A),
+ (orisadd AddrFI:$Rs, ImmPred:$Off)),
+ (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
+}
+
+multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
+ SDNode Oper, InstHexagon MI> {
+ defm: Memopxr_simple_pat <Load, Store, Oper, MI>;
+ defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>;
+}
+
+let AddedComplexity = 180 in {
+ // add reg
+ defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add,
+ /*anyext*/ L4_add_memopb_io>;
+ defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add,
+ /*sext*/ L4_add_memopb_io>;
+ defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add,
+ /*zext*/ L4_add_memopb_io>;
+ defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add,
+ /*anyext*/ L4_add_memoph_io>;
+ defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add,
+ /*sext*/ L4_add_memoph_io>;
+ defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add,
+ /*zext*/ L4_add_memoph_io>;
+ defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>;
+
+ // sub reg
+ defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub,
+ /*anyext*/ L4_sub_memopb_io>;
+ defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub,
+ /*sext*/ L4_sub_memopb_io>;
+ defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub,
+ /*zext*/ L4_sub_memopb_io>;
+ defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub,
+ /*anyext*/ L4_sub_memoph_io>;
+ defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub,
+ /*sext*/ L4_sub_memoph_io>;
+ defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub,
+ /*zext*/ L4_sub_memoph_io>;
+ defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>;
+
+ // and reg
+ defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and,
+ /*anyext*/ L4_and_memopb_io>;
+ defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and,
+ /*sext*/ L4_and_memopb_io>;
+ defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and,
+ /*zext*/ L4_and_memopb_io>;
+ defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and,
+ /*anyext*/ L4_and_memoph_io>;
+ defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and,
+ /*sext*/ L4_and_memoph_io>;
+ defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and,
+ /*zext*/ L4_and_memoph_io>;
+ defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>;
+
+ // or reg
+ defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or,
+ /*anyext*/ L4_or_memopb_io>;
+ defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or,
+ /*sext*/ L4_or_memopb_io>;
+ defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or,
+ /*zext*/ L4_or_memopb_io>;
+ defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or,
+ /*anyext*/ L4_or_memoph_io>;
+ defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or,
+ /*sext*/ L4_or_memoph_io>;
+ defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or,
+ /*zext*/ L4_or_memoph_io>;
+ defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>;
+}
+
+
+multiclass Memopxi_simple_pat<PatFrag Load, PatFrag Store, SDNode Oper,
+ PatFrag Arg, SDNodeXForm ArgMod,
+ InstHexagon MI> {
+ // Addr: i32
+ def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs),
+ (MI I32:$Rs, 0, (ArgMod Arg:$A))>;
+ // Addr: fi
+ def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs),
+ (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>;
+}
+
+multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
+ SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod,
+ InstHexagon MI> {
+ // Addr: i32
+ def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A),
+ (add I32:$Rs, ImmPred:$Off)),
+ (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
+ def: Pat<(Store (Oper (Load (orisadd I32:$Rs, ImmPred:$Off)), Arg:$A),
+ (orisadd I32:$Rs, ImmPred:$Off)),
+ (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
+ // Addr: fi
+ def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A),
+ (add AddrFI:$Rs, ImmPred:$Off)),
+ (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
+ def: Pat<(Store (Oper (Load (orisadd AddrFI:$Rs, ImmPred:$Off)), Arg:$A),
+ (orisadd AddrFI:$Rs, ImmPred:$Off)),
+ (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
+}
+
+multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
+ SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod,
+ InstHexagon MI> {
+ defm: Memopxi_simple_pat <Load, Store, Oper, Arg, ArgMod, MI>;
+ defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>;
+}
+
+
+let AddedComplexity = 200 in {
+ // add imm
+ defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5ImmPred,
+ /*anyext*/ IdImm, L4_iadd_memopb_io>;
+ defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5ImmPred,
+ /*sext*/ IdImm, L4_iadd_memopb_io>;
+ defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5ImmPred,
+ /*zext*/ IdImm, L4_iadd_memopb_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5ImmPred,
+ /*anyext*/ IdImm, L4_iadd_memoph_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5ImmPred,
+ /*sext*/ IdImm, L4_iadd_memoph_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5ImmPred,
+ /*zext*/ IdImm, L4_iadd_memoph_io>;
+ defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5ImmPred, IdImm,
+ L4_iadd_memopw_io>;
+ defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5Imm8Pred,
+ /*anyext*/ NegImm8, L4_iadd_memopb_io>;
+ defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5Imm8Pred,
+ /*sext*/ NegImm8, L4_iadd_memopb_io>;
+ defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5Imm8Pred,
+ /*zext*/ NegImm8, L4_iadd_memopb_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5Imm16Pred,
+ /*anyext*/ NegImm16, L4_iadd_memoph_io>;
+ defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5Imm16Pred,
+ /*sext*/ NegImm16, L4_iadd_memoph_io>;
+ defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5Imm16Pred,
+ /*zext*/ NegImm16, L4_iadd_memoph_io>;
+ defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5ImmPred, NegImm32,
+ L4_iadd_memopw_io>;
+
+ // sub imm
+ defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5ImmPred,
+ /*anyext*/ IdImm, L4_isub_memopb_io>;
+ defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5ImmPred,
+ /*sext*/ IdImm, L4_isub_memopb_io>;
+ defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5ImmPred,
+ /*zext*/ IdImm, L4_isub_memopb_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5ImmPred,
+ /*anyext*/ IdImm, L4_isub_memoph_io>;
+ defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5ImmPred,
+ /*sext*/ IdImm, L4_isub_memoph_io>;
+ defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5ImmPred,
+ /*zext*/ IdImm, L4_isub_memoph_io>;
+ defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5ImmPred, IdImm,
+ L4_isub_memopw_io>;
+ defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5Imm8Pred,
+ /*anyext*/ NegImm8, L4_isub_memopb_io>;
+ defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5Imm8Pred,
+ /*sext*/ NegImm8, L4_isub_memopb_io>;
+ defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5Imm8Pred,
+ /*zext*/ NegImm8, L4_isub_memopb_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5Imm16Pred,
+ /*anyext*/ NegImm16, L4_isub_memoph_io>;
+ defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5Imm16Pred,
+ /*sext*/ NegImm16, L4_isub_memoph_io>;
+ defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5Imm16Pred,
+ /*zext*/ NegImm16, L4_isub_memoph_io>;
+ defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5ImmPred, NegImm32,
+ L4_isub_memopw_io>;
+
+ // clrbit imm
+ defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, Clr5Imm8Pred,
+ /*anyext*/ Clr5Imm8, L4_iand_memopb_io>;
+ defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, Clr5Imm8Pred,
+ /*sext*/ Clr5Imm8, L4_iand_memopb_io>;
+ defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, Clr5Imm8Pred,
+ /*zext*/ Clr5Imm8, L4_iand_memopb_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, Clr5Imm16Pred,
+ /*anyext*/ Clr5Imm16, L4_iand_memoph_io>;
+ defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, Clr5Imm16Pred,
+ /*sext*/ Clr5Imm16, L4_iand_memoph_io>;
+ defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, Clr5Imm16Pred,
+ /*zext*/ Clr5Imm16, L4_iand_memoph_io>;
+ defm: Memopxi_pat<load, store, u6_2ImmPred, and, Clr5ImmPred, Clr5Imm16,
+ L4_iand_memopw_io>;
+
+ // setbit imm
+ defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, Set5ImmPred,
+ /*anyext*/ Set5Imm8, L4_ior_memopb_io>;
+ defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, Set5ImmPred,
+ /*sext*/ Set5Imm8, L4_ior_memopb_io>;
+ defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, Set5ImmPred,
+ /*zext*/ Set5Imm8, L4_ior_memopb_io>;
+ defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, Set5ImmPred,
+ /*anyext*/ Set5Imm16, L4_ior_memoph_io>;
+ defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, Set5ImmPred,
+ /*sext*/ Set5Imm16, L4_ior_memoph_io>;
+ defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, Set5ImmPred,
+ /*zext*/ Set5Imm16, L4_ior_memoph_io>;
+ defm: Memopxi_pat<load, store, u6_2ImmPred, or, Set5ImmPred, Set5Imm32,
+ L4_ior_memopw_io>;
}
//===----------------------------------------------------------------------===//
@@ -3846,7 +3914,7 @@ let AddedComplexity = 30 in {
// Indexed store word - global address.
// memw(Rs+#u6:2)=#S8
let AddedComplexity = 100 in
-def: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
+defm: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
// Load from a global address that has only one use in the current basic block.
let AddedComplexity = 100 in {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOperands.td?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOperands.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOperands.td Fri Jul 15 10:35:52 2016
@@ -347,22 +347,6 @@ def u1ImmPred32 : PatLeaf<(i32 imm), [{
return isUInt<1>(v);
}]>;
-def m5BImmPred : PatLeaf<(i32 imm), [{
- // m5BImmPred predicate - True if the (char) number is in range -1 .. -31
- // and will fit in a 5 bit field when made positive, for use in memops.
- // this is specific to the zero extending of a negative by CombineInstr
- int8_t v = (int8_t)N->getSExtValue();
- return (-31 <= v && v <= -1);
-}]>;
-
-def m5HImmPred : PatLeaf<(i32 imm), [{
- // m5HImmPred predicate - True if the (short) number is in range -1 .. -31
- // and will fit in a 5 bit field when made positive, for use in memops.
- // this is specific to the zero extending of a negative by CombineInstr
- int16_t v = (int16_t)N->getSExtValue();
- return (-31 <= v && v <= -1);
-}]>;
-
def m5ImmPred : PatLeaf<(i32 imm), [{
// m5ImmPred predicate - True if the number is in range -1 .. -31
// and will fit in a 5 bit field when made positive, for use in memops.
@@ -404,60 +388,6 @@ def Clr5ImmPred : PatLeaf<(i32 imm), [{
return ImmIsSingleBit(v);
}]>;
-def SetClr5ImmPred : PatLeaf<(i32 imm), [{
- // True if the immediate is in range 0..31.
- int32_t v = (int32_t)N->getSExtValue();
- return (v >= 0 && v <= 31);
-}]>;
-
-def Set4ImmPred : PatLeaf<(i32 imm), [{
- // Set4ImmPred predicate - True if the number is in the series of values:
- // [ 2^0, 2^1, ... 2^15 ].
- // For use in setbit immediate.
- uint16_t v = (int16_t)N->getSExtValue();
- // Constrain to 16 bits, and then check for single bit.
- return ImmIsSingleBit(v);
-}]>;
-
-def Clr4ImmPred : PatLeaf<(i32 imm), [{
- // Clr4ImmPred predicate - True if the number is in the series of
- // bit negated values:
- // [ 2^0, 2^1, ... 2^15 ].
- // For use in setbit and clrbit immediate.
- uint16_t v = ~ (int16_t)N->getSExtValue();
- // Constrain to 16 bits, and then check for single bit.
- return ImmIsSingleBit(v);
-}]>;
-
-def SetClr4ImmPred : PatLeaf<(i32 imm), [{
- // True if the immediate is in the range 0..15.
- int16_t v = (int16_t)N->getSExtValue();
- return (v >= 0 && v <= 15);
-}]>;
-
-def Set3ImmPred : PatLeaf<(i32 imm), [{
- // True if the number is in the series of values: [ 2^0, 2^1, ... 2^7 ].
- // For use in setbit immediate.
- uint8_t v = (int8_t)N->getSExtValue();
- // Constrain to 8 bits, and then check for single bit.
- return ImmIsSingleBit(v);
-}]>;
-
-def Clr3ImmPred : PatLeaf<(i32 imm), [{
- // True if the number is in the series of bit negated values: [ 2^0, 2^1, ... 2^7 ].
- // For use in setbit and clrbit immediate.
- uint8_t v = ~ (int8_t)N->getSExtValue();
- // Constrain to 8 bits, and then check for single bit.
- return ImmIsSingleBit(v);
-}]>;
-
-def SetClr3ImmPred : PatLeaf<(i32 imm), [{
- // True if the immediate is in the range 0..7.
- int8_t v = (int8_t)N->getSExtValue();
- return (v >= 0 && v <= 7);
-}]>;
-
-
// Extendable immediate operands.
def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
def s16ExtOperand : AsmOperandClass { let Name = "s16Ext"; }
Modified: llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll Fri Jul 15 10:35:52 2016
@@ -3,6 +3,7 @@
define i32 @my_clrbit(i32 %x) nounwind {
entry:
+; CHECK-LABEL: my_clrbit
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
@@ -13,6 +14,7 @@ entry:
define i64 @my_clrbit2(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_clrbit2
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -23,6 +25,7 @@ entry:
define i64 @my_clrbit3(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_clrbit3
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -33,6 +36,7 @@ entry:
define i32 @my_clrbit4(i32 %x) nounwind {
entry:
+; CHECK-LABEL: my_clrbit4
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
@@ -43,6 +47,7 @@ entry:
define i64 @my_clrbit5(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_clrbit5
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -53,6 +58,7 @@ entry:
define i64 @my_clrbit6(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_clrbit6
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -63,7 +69,8 @@ entry:
define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
entry:
-; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15)
+; CHECK-LABEL: my_setbit
+; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}){{ *}}={{ *}}setbit(#15)
%crc.addr = alloca i16, align 2
store i16 %crc, i16* %crc.addr, align 2
%0 = load i16, i16* %crc.addr, align 2
@@ -77,6 +84,7 @@ entry:
define i32 @my_setbit2(i32 %x) nounwind {
entry:
+; CHECK-LABEL: my_setbit2
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
@@ -87,6 +95,7 @@ entry:
define i64 @my_setbit3(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_setbit3
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -97,6 +106,7 @@ entry:
define i32 @my_setbit4(i32 %x) nounwind {
entry:
+; CHECK-LABEL: my_setbit4
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
@@ -107,6 +117,7 @@ entry:
define i64 @my_setbit5(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_setbit5
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -117,6 +128,7 @@ entry:
define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
entry:
+; CHECK-LABEL: my_togglebit
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
%crc.addr = alloca i16, align 2
store i16 %crc, i16* %crc.addr, align 2
@@ -131,6 +143,7 @@ entry:
define i32 @my_togglebit2(i32 %x) nounwind {
entry:
+; CHECK-LABEL: my_togglebit2
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
@@ -141,6 +154,7 @@ entry:
define i64 @my_togglebit3(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_togglebit3
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
@@ -151,6 +165,7 @@ entry:
define i64 @my_togglebit4(i64 %x) nounwind {
entry:
+; CHECK-LABEL: my_togglebit4
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
Added: llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll?rev=275569&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/memops-stack.ll Fri Jul 15 10:35:52 2016
@@ -0,0 +1,147 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+; CHECK-LABEL: test0
+; CHECK: memw(r29+#{{[0-9]+}}) += #1
+define void @test0() #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = add nsw i32 %1, 1
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test1
+; CHECK: memw(r29+#{{[0-9]+}}) -= #1
+define void @test1() #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = sub nsw i32 %1, 1
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test2
+; CHECK: memw(r29+#{{[0-9]+}}) = setbit(#0)
+define void @test2() #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = or i32 %1, 1
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test3
+; CHECK: memw(r29+#{{[0-9]+}}) = clrbit(#0)
+define void @test3() #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = and i32 %1, -2
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test4
+; CHECK: memw(r29+#{{[0-9]+}}) += r
+define void @test4(i32 %a) #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = add nsw i32 %1, %a
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test5
+; CHECK: memw(r29+#{{[0-9]+}}) -= r
+define void @test5(i32 %a) #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = sub nsw i32 %1, %a
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test6
+; CHECK: memw(r29+#{{[0-9]+}}) |= r
+define void @test6(i32 %a) #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = or i32 %1, %a
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+; CHECK-LABEL: test7
+; CHECK: memw(r29+#{{[0-9]+}}) &= r
+define void @test7(i32 %a) #0 {
+entry:
+ %x = alloca i32, align 4
+ %0 = bitcast i32* %x to i8*
+ call void @llvm.lifetime.start(i64 4, i8* %0) #3
+ call void @foo(i32* nonnull %x) #3
+ %1 = load i32, i32* %x, align 4, !tbaa !1
+ %inc = and i32 %1, %a
+ store i32 %inc, i32* %x, align 4, !tbaa !1
+ call void @foo(i32* nonnull %x) #3
+ call void @llvm.lifetime.end(i64 4, i8* %0) #3
+ ret void
+}
+
+
+declare void @foo(i32*) #2
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind }
+attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind }
+
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
Modified: llvm/trunk/test/CodeGen/Hexagon/memops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/memops.ll?rev=275569&r1=275568&r2=275569&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/memops.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/memops.ll Fri Jul 15 10:35:52 2016
@@ -3,6 +3,7 @@
define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_add5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%0 = load i8, i8* %p, align 1
%conv = zext i8 %0 to i32
@@ -14,6 +15,7 @@ entry:
define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_add:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv = zext i8 %x to i32
%0 = load i8, i8* %p, align 1
@@ -26,6 +28,7 @@ entry:
define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_sub:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv = zext i8 %x to i32
%0 = load i8, i8* %p, align 1
@@ -38,6 +41,7 @@ entry:
define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_or:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%0 = load i8, i8* %p, align 1
%or3 = or i8 %0, %x
@@ -47,6 +51,7 @@ entry:
define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_and:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%0 = load i8, i8* %p, align 1
%and3 = and i8 %0, %x
@@ -56,6 +61,7 @@ entry:
define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_clrbit:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%0 = load i8, i8* %p, align 1
%conv = zext i8 %0 to i32
@@ -67,6 +73,7 @@ entry:
define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_setbit:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%0 = load i8, i8* %p, align 1
%conv = zext i8 %0 to i32
@@ -78,6 +85,7 @@ entry:
define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_add5_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -90,6 +98,7 @@ entry:
define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_add_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
@@ -103,6 +112,7 @@ entry:
define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_sub_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
@@ -116,6 +126,7 @@ entry:
define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_or_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -126,6 +137,7 @@ entry:
define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_and_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -136,6 +148,7 @@ entry:
define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_clrbit_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -148,6 +161,7 @@ entry:
define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_setbit_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -160,6 +174,7 @@ entry:
define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_add5_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -172,6 +187,7 @@ entry:
define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_add_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
%conv = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
@@ -185,6 +201,7 @@ entry:
define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_sub_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
%conv = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
@@ -198,6 +215,7 @@ entry:
define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_or_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -208,6 +226,7 @@ entry:
define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_and_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -218,6 +237,7 @@ entry:
define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_clrbit_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -230,6 +250,7 @@ entry:
define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_char_setbit_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -242,6 +263,7 @@ entry:
define void @memop_signed_char_add5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_add5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%0 = load i8, i8* %p, align 1
%conv2 = zext i8 %0 to i32
@@ -253,6 +275,7 @@ entry:
define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_add:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv4 = zext i8 %x to i32
%0 = load i8, i8* %p, align 1
@@ -265,6 +288,7 @@ entry:
define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_sub:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv4 = zext i8 %x to i32
%0 = load i8, i8* %p, align 1
@@ -277,6 +301,7 @@ entry:
define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_or:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%0 = load i8, i8* %p, align 1
%or3 = or i8 %0, %x
@@ -286,6 +311,7 @@ entry:
define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_and:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%0 = load i8, i8* %p, align 1
%and3 = and i8 %0, %x
@@ -295,6 +321,7 @@ entry:
define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_clrbit:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%0 = load i8, i8* %p, align 1
%conv2 = zext i8 %0 to i32
@@ -306,6 +333,7 @@ entry:
define void @memop_signed_char_setbit(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_setbit:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%0 = load i8, i8* %p, align 1
%conv2 = zext i8 %0 to i32
@@ -317,6 +345,7 @@ entry:
define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_add5_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -329,6 +358,7 @@ entry:
define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_add_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv4 = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
@@ -342,6 +372,7 @@ entry:
define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_sub_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv4 = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
@@ -355,6 +386,7 @@ entry:
define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_or_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -365,6 +397,7 @@ entry:
define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_and_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -375,6 +408,7 @@ entry:
define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_clrbit_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -387,6 +421,7 @@ entry:
define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_setbit_index:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
%0 = load i8, i8* %add.ptr, align 1
@@ -399,6 +434,7 @@ entry:
define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_add5_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -411,6 +447,7 @@ entry:
define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_add_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
%conv4 = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
@@ -424,6 +461,7 @@ entry:
define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_sub_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
%conv4 = zext i8 %x to i32
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
@@ -437,6 +475,7 @@ entry:
define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_or_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -447,6 +486,7 @@ entry:
define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_and_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -457,6 +497,7 @@ entry:
define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_clrbit_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -469,6 +510,7 @@ entry:
define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_char_setbit_index5:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i8, i8* %p, i32 5
%0 = load i8, i8* %add.ptr, align 1
@@ -481,6 +523,7 @@ entry:
define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_add5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%0 = load i16, i16* %p, align 2
%conv = zext i16 %0 to i32
@@ -492,6 +535,7 @@ entry:
define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_add:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv = zext i16 %x to i32
%0 = load i16, i16* %p, align 2
@@ -504,6 +548,7 @@ entry:
define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_sub:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv = zext i16 %x to i32
%0 = load i16, i16* %p, align 2
@@ -516,6 +561,7 @@ entry:
define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_or:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%0 = load i16, i16* %p, align 2
%or3 = or i16 %0, %x
@@ -525,6 +571,7 @@ entry:
define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_and:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%0 = load i16, i16* %p, align 2
%and3 = and i16 %0, %x
@@ -534,6 +581,7 @@ entry:
define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_clrbit:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%0 = load i16, i16* %p, align 2
%conv = zext i16 %0 to i32
@@ -545,6 +593,7 @@ entry:
define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_setbit:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%0 = load i16, i16* %p, align 2
%conv = zext i16 %0 to i32
@@ -556,6 +605,7 @@ entry:
define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_add5_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -568,6 +618,7 @@ entry:
define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_add_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
@@ -581,6 +632,7 @@ entry:
define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_sub_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
@@ -594,6 +646,7 @@ entry:
define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_or_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -604,6 +657,7 @@ entry:
define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_and_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -614,6 +668,7 @@ entry:
define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_clrbit_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -626,6 +681,7 @@ entry:
define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_setbit_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -638,6 +694,7 @@ entry:
define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_add5_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -650,6 +707,7 @@ entry:
define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_add_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
%conv = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
@@ -663,6 +721,7 @@ entry:
define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_sub_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
%conv = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
@@ -676,6 +735,7 @@ entry:
define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_or_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -686,6 +746,7 @@ entry:
define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_and_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -696,6 +757,7 @@ entry:
define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_clrbit_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -708,6 +770,7 @@ entry:
define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_short_setbit_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -720,6 +783,7 @@ entry:
define void @memop_signed_short_add5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_add5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%0 = load i16, i16* %p, align 2
%conv2 = zext i16 %0 to i32
@@ -731,6 +795,7 @@ entry:
define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_add:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv4 = zext i16 %x to i32
%0 = load i16, i16* %p, align 2
@@ -743,6 +808,7 @@ entry:
define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_sub:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv4 = zext i16 %x to i32
%0 = load i16, i16* %p, align 2
@@ -755,6 +821,7 @@ entry:
define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_or:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%0 = load i16, i16* %p, align 2
%or3 = or i16 %0, %x
@@ -764,6 +831,7 @@ entry:
define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_and:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%0 = load i16, i16* %p, align 2
%and3 = and i16 %0, %x
@@ -773,6 +841,7 @@ entry:
define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_clrbit:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%0 = load i16, i16* %p, align 2
%conv2 = zext i16 %0 to i32
@@ -784,6 +853,7 @@ entry:
define void @memop_signed_short_setbit(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_setbit:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%0 = load i16, i16* %p, align 2
%conv2 = zext i16 %0 to i32
@@ -795,6 +865,7 @@ entry:
define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_add5_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -807,6 +878,7 @@ entry:
define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_add_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%conv4 = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
@@ -820,6 +892,7 @@ entry:
define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_sub_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%conv4 = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
@@ -833,6 +906,7 @@ entry:
define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_or_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -843,6 +917,7 @@ entry:
define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_and_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -853,6 +928,7 @@ entry:
define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_clrbit_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -865,6 +941,7 @@ entry:
define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_setbit_index:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
%0 = load i16, i16* %add.ptr, align 2
@@ -877,6 +954,7 @@ entry:
define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_add5_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -889,6 +967,7 @@ entry:
define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_add_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
%conv4 = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
@@ -902,6 +981,7 @@ entry:
define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_sub_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
%conv4 = zext i16 %x to i32
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
@@ -915,6 +995,7 @@ entry:
define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_or_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -925,6 +1006,7 @@ entry:
define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_and_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -935,6 +1017,7 @@ entry:
define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_clrbit_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -947,6 +1030,7 @@ entry:
define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_short_setbit_index5:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i16, i16* %p, i32 5
%0 = load i16, i16* %add.ptr, align 2
@@ -959,6 +1043,7 @@ entry:
define void @memop_signed_int_add5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_add5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%0 = load i32, i32* %p, align 4
%add = add i32 %0, 5
@@ -968,6 +1053,7 @@ entry:
define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_add:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%add = add i32 %0, %x
@@ -977,6 +1063,7 @@ entry:
define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_sub:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%sub = sub i32 %0, %x
@@ -986,6 +1073,7 @@ entry:
define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_or:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%or = or i32 %0, %x
@@ -995,6 +1083,7 @@ entry:
define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_and:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%and = and i32 %0, %x
@@ -1004,6 +1093,7 @@ entry:
define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_clrbit:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%0 = load i32, i32* %p, align 4
%and = and i32 %0, -33
@@ -1013,6 +1103,7 @@ entry:
define void @memop_signed_int_setbit(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_setbit:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%0 = load i32, i32* %p, align 4
%or = or i32 %0, 128
@@ -1022,6 +1113,7 @@ entry:
define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_add5_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1032,6 +1124,7 @@ entry:
define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_add_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1042,6 +1135,7 @@ entry:
define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_sub_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1052,6 +1146,7 @@ entry:
define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_or_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1062,6 +1157,7 @@ entry:
define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_and_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1072,6 +1168,7 @@ entry:
define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_clrbit_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1082,6 +1179,7 @@ entry:
define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_setbit_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1092,6 +1190,7 @@ entry:
define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_add5_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1102,6 +1201,7 @@ entry:
define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_add_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1112,6 +1212,7 @@ entry:
define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_sub_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1122,6 +1223,7 @@ entry:
define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_or_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1132,6 +1234,7 @@ entry:
define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_and_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1142,6 +1245,7 @@ entry:
define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_clrbit_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1152,6 +1256,7 @@ entry:
define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_signed_int_setbit_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1162,6 +1267,7 @@ entry:
define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_add5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%0 = load i32, i32* %p, align 4
%add = add nsw i32 %0, 5
@@ -1171,6 +1277,7 @@ entry:
define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_add:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%add = add nsw i32 %0, %x
@@ -1180,6 +1287,7 @@ entry:
define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_sub:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%sub = sub nsw i32 %0, %x
@@ -1189,6 +1297,7 @@ entry:
define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_or:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%or = or i32 %0, %x
@@ -1198,6 +1307,7 @@ entry:
define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_and:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%0 = load i32, i32* %p, align 4
%and = and i32 %0, %x
@@ -1207,6 +1317,7 @@ entry:
define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_clrbit:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%0 = load i32, i32* %p, align 4
%and = and i32 %0, -33
@@ -1216,6 +1327,7 @@ entry:
define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_setbit:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%0 = load i32, i32* %p, align 4
%or = or i32 %0, 128
@@ -1225,6 +1337,7 @@ entry:
define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_add5_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1235,6 +1348,7 @@ entry:
define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_add_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1245,6 +1359,7 @@ entry:
define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_sub_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1255,6 +1370,7 @@ entry:
define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_or_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1265,6 +1381,7 @@ entry:
define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_and_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1275,6 +1392,7 @@ entry:
define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_clrbit_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1285,6 +1403,7 @@ entry:
define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_setbit_index:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
%0 = load i32, i32* %add.ptr, align 4
@@ -1295,6 +1414,7 @@ entry:
define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_add5_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1305,6 +1425,7 @@ entry:
define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_add_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1315,6 +1436,7 @@ entry:
define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_sub_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1325,6 +1447,7 @@ entry:
define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_or_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1335,6 +1458,7 @@ entry:
define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_and_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1345,6 +1469,7 @@ entry:
define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_clrbit_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
@@ -1355,6 +1480,7 @@ entry:
define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind {
entry:
+; CHECK-LABEL: memop_unsigned_int_setbit_index5:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
%add.ptr = getelementptr inbounds i32, i32* %p, i32 5
%0 = load i32, i32* %add.ptr, align 4
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