[PATCH] D22398: MIRParser: Allow register class specification on operand

[Matthias Braun via llvm-commits]

MatzeB created this revision.
MatzeB added reviewers: qcolombet, arphaman.
MatzeB added a subscriber: llvm-commits.
MatzeB set the repository for this revision to rL LLVM.
Herald added a subscriber: mcrosier.

You can now define the register class of a virtual register on the
operand itself avoiding the need to use a "registers:" block.

Example: "%0:gr64 = COPY %rax"

Repository:
  rL LLVM

https://reviews.llvm.org/D22398

Files:
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRParser/MIParser.h
  lib/CodeGen/MIRParser/MIRParser.cpp
  test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
  test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
  test/CodeGen/MIR/X86/register-operand-class.mir

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