[llvm] r275410 - [mips] SelectionDAGISel subclasses now follow the optimization level.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 06:25:22 PDT 2016
Author: dsanders
Date: Thu Jul 14 08:25:22 2016
New Revision: 275410
URL: http://llvm.org/viewvc/llvm-project?rev=275410&view=rev
Log:
[mips] SelectionDAGISel subclasses now follow the optimization level.
Summary:
It was recently discovered that, for Mips's SelectionDAGISel subclasses,
all optimization levels caused SelectionDAGISel to behave like -O2.
This change adds the necessary plumbing to initialize the optimization level.
Reviewers: andrew.w.kaylor
Subscribers: andrew.w.kaylor, sdardis, dean, llvm-commits, vradosavljevic, petarj, qcolombet, probinson, dsanders
Differential Revision: https://reviews.llvm.org/D14900
Added:
llvm/trunk/test/CodeGen/Mips/selectiondag-optlevel.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
Modified: llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp?rev=275410&r1=275409&r2=275410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp Thu Jul 14 08:25:22 2016
@@ -254,6 +254,7 @@ bool Mips16DAGToDAGISel::trySelect(SDNod
return false;
}
-FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
- return new Mips16DAGToDAGISel(TM);
+FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM,
+ CodeGenOpt::Level OptLevel) {
+ return new Mips16DAGToDAGISel(TM, OptLevel);
}
Modified: llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h?rev=275410&r1=275409&r2=275410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h Thu Jul 14 08:25:22 2016
@@ -20,7 +20,8 @@ namespace llvm {
class Mips16DAGToDAGISel : public MipsDAGToDAGISel {
public:
- explicit Mips16DAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {}
+ explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+ : MipsDAGToDAGISel(TM, OL) {}
private:
std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
@@ -47,7 +48,8 @@ private:
void initMips16SPAliasReg(MachineFunction &MF);
};
-FunctionPass *createMips16ISelDag(MipsTargetMachine &TM);
+FunctionPass *createMips16ISelDag(MipsTargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
}
#endif
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h?rev=275410&r1=275409&r2=275410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h Thu Jul 14 08:25:22 2016
@@ -31,8 +31,8 @@ namespace llvm {
class MipsDAGToDAGISel : public SelectionDAGISel {
public:
- explicit MipsDAGToDAGISel(MipsTargetMachine &TM)
- : SelectionDAGISel(TM), Subtarget(nullptr) {}
+ explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+ : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
// Pass Name
const char *getPassName() const override {
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=275410&r1=275409&r2=275410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Thu Jul 14 08:25:22 2016
@@ -1033,6 +1033,7 @@ SelectInlineAsmMemoryOperand(const SDVal
return true;
}
-FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
- return new MipsSEDAGToDAGISel(TM);
+FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
+ CodeGenOpt::Level OptLevel) {
+ return new MipsSEDAGToDAGISel(TM, OptLevel);
}
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h?rev=275410&r1=275409&r2=275410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h Thu Jul 14 08:25:22 2016
@@ -21,7 +21,8 @@ namespace llvm {
class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
public:
- explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {}
+ explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+ : MipsDAGToDAGISel(TM, OL) {}
private:
@@ -131,8 +132,8 @@ private:
std::vector<SDValue> &OutOps) override;
};
-FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM);
-
+FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
}
#endif
Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=275410&r1=275409&r2=275410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 14 08:25:22 2016
@@ -229,8 +229,8 @@ void MipsPassConfig::addIRPasses() {
// the ISelDag to gen Mips code.
bool MipsPassConfig::addInstSelector() {
addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
- addPass(createMips16ISelDag(getMipsTargetMachine()));
- addPass(createMipsSEISelDag(getMipsTargetMachine()));
+ addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
+ addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
return false;
}
Added: llvm/trunk/test/CodeGen/Mips/selectiondag-optlevel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/selectiondag-optlevel.ll?rev=275410&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/selectiondag-optlevel.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/selectiondag-optlevel.ll Thu Jul 14 08:25:22 2016
@@ -0,0 +1,22 @@
+; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0
+; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2
+
+; At -O0, DAGCombine won't try to merge these consecutive loads but it will at
+; -O2.
+
+define void @foo() nounwind {
+entry:
+ %0 = alloca [2 x i8], align 32
+ %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0
+ store i8 1, i8* %1
+ %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1
+ store i8 1, i8* %2
+ ret void
+}
+
+; O0: addiu $[[REG:[0-9]+]], $zero, 1
+; O0-DAG: sb $[[REG]], 0($sp)
+; O0-DAG: sb $[[REG]], 1($sp)
+
+; O2: addiu $[[REG:[0-9]+]], $zero, 257
+; O2: sh $[[REG]], 0($sp)
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