[llvm] r275200 - AMDGPU: Set isConvergent on v_cmpx* instructions

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Tue Jul 12 13:41:03 2016
New Revision: 275200

URL: http://llvm.org/viewvc/llvm-project?rev=275200&view=rev
Log:
AMDGPU: Set isConvergent on v_cmpx* instructions

No test since these aren't used now, except for one place
in a pre-emit pass.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=275200&r1=275199&r2=275200&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Tue Jul 12 13:41:03 2016
@@ -2303,13 +2303,14 @@ multiclass VOPC_m <vopc op, dag ins, str
            VOP2_REV<revOpName#"_e32", !eq(revOpName, opName)> {
     let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
     let SchedRW = sched;
+    let isConvergent = DefExec;
   }
 
   let AssemblerPredicates = [isSICI] in {
     def _si : VOPC<op.SI, ins, asm, []>,
               SIMCInstr <opName#"_e32", SIEncodingFamily.SI> {
       let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
-      let hasSideEffects = DefExec;
+      let isConvergent = DefExec;
       let SchedRW = sched;
       let DecoderNamespace = "SICI";
       let DisableDecoder = DisableSIDecoder;
@@ -2321,7 +2322,7 @@ multiclass VOPC_m <vopc op, dag ins, str
     def _vi : VOPC<op.VI, ins, asm, []>,
               SIMCInstr <opName#"_e32", SIEncodingFamily.VI> {
       let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
-      let hasSideEffects = DefExec;
+      let isConvergent = DefExec;
       let SchedRW = sched;
       let DecoderNamespace = "VI";
       let DisableDecoder = DisableVIDecoder;