[PATCH] D22251: [MIR] Print the regular output of mir in the output file

Mon Jul 11 18:27:32 PDT 2016

qcolombet created this revision.
qcolombet added a reviewer: MatzeB.
qcolombet added a subscriber: llvm-commits.
qcolombet set the repository for this revision to rL LLVM.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: nemanjai, dsanders, qcolombet, jholewinski.

Hi,

Currently the MIR framework prints all its outputs (errors and actual representation) on stderr.

This patch fixes that by printing the regular output in the output specified with -o.

The patch itself is pretty straightforward but a lot of tests have to be updated, that’s why I put up a review.
Basically, every test that uses mir needs to be updated to:
1. Replace -o /dev/null into -o -
2. Get rid of the useless 2>&1

The change is pretty mechanical.

Repository:
  rL LLVM

http://reviews.llvm.org/D22251

Files:
  lib/CodeGen/LLVMTargetMachine.cpp
  test/CodeGen/AArch64/branch-folder-merge-mmos.ll
  test/CodeGen/AArch64/stackmap-frame-setup.ll
  test/CodeGen/AMDGPU/detect-dead-lanes.mir
  test/CodeGen/AMDGPU/indirect-addressing-undef.mir
  test/CodeGen/AMDGPU/rename-independent-subregs.mir
  test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
  test/CodeGen/ARM/thumb1-ldst-opt.ll
  test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
  test/CodeGen/MIR/AArch64/machine-dead-copy.mir
  test/CodeGen/MIR/AArch64/machine-scheduler.mir
  test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
  test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
  test/CodeGen/MIR/AArch64/target-flags.mir
  test/CodeGen/MIR/AMDGPU/target-index-operands.mir
  test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir
  test/CodeGen/MIR/ARM/bundled-instructions.mir
  test/CodeGen/MIR/ARM/cfi-same-value.mir
  test/CodeGen/MIR/ARM/imm-peephole-arm.mir
  test/CodeGen/MIR/ARM/imm-peephole-thumb.mir
  test/CodeGen/MIR/Generic/basic-blocks.mir
  test/CodeGen/MIR/Generic/frame-info.mir
  test/CodeGen/MIR/Generic/llvmIR.mir
  test/CodeGen/MIR/Generic/llvmIRMissing.mir
  test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
  test/CodeGen/MIR/Generic/machine-function.mir
  test/CodeGen/MIR/Generic/multiRunPass.mir
  test/CodeGen/MIR/Generic/register-info.mir
  test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
  test/CodeGen/MIR/Lanai/peephole-compare.mir
  test/CodeGen/MIR/Mips/memory-operands.mir
  test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
  test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
  test/CodeGen/MIR/X86/basic-block-liveins.mir
  test/CodeGen/MIR/X86/block-address-operands.mir
  test/CodeGen/MIR/X86/callee-saved-info.mir
  test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
  test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
  test/CodeGen/MIR/X86/cfi-offset.mir
  test/CodeGen/MIR/X86/constant-pool.mir
  test/CodeGen/MIR/X86/dead-register-flag.mir
  test/CodeGen/MIR/X86/early-clobber-register-flag.mir
  test/CodeGen/MIR/X86/external-symbol-operands.mir
  test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
  test/CodeGen/MIR/X86/fixed-stack-objects.mir
  test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
  test/CodeGen/MIR/X86/frame-info-stack-references.mir
  test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
  test/CodeGen/MIR/X86/function-liveins.mir
  test/CodeGen/MIR/X86/generic-virtual-registers.mir
  test/CodeGen/MIR/X86/global-value-operands.mir
  test/CodeGen/MIR/X86/immediate-operands.mir
  test/CodeGen/MIR/X86/implicit-register-flag.mir
  test/CodeGen/MIR/X86/inline-asm-registers.mir
  test/CodeGen/MIR/X86/instructions-debug-location.mir
  test/CodeGen/MIR/X86/jump-table-info.mir
  test/CodeGen/MIR/X86/killed-register-flag.mir
  test/CodeGen/MIR/X86/liveout-register-mask.mir
  test/CodeGen/MIR/X86/machine-basic-block-operands.mir
  test/CodeGen/MIR/X86/machine-instructions.mir
  test/CodeGen/MIR/X86/memory-operands.mir
  test/CodeGen/MIR/X86/metadata-operands.mir
  test/CodeGen/MIR/X86/named-registers.mir
  test/CodeGen/MIR/X86/newline-handling.mir
  test/CodeGen/MIR/X86/null-register-operands.mir
  test/CodeGen/MIR/X86/register-mask-operands.mir
  test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
  test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
  test/CodeGen/MIR/X86/stack-object-debug-info.mir
  test/CodeGen/MIR/X86/stack-object-operands.mir
  test/CodeGen/MIR/X86/stack-objects.mir
  test/CodeGen/MIR/X86/subregister-index-operands.mir
  test/CodeGen/MIR/X86/subregister-operands.mir
  test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
  test/CodeGen/MIR/X86/successor-basic-blocks.mir
  test/CodeGen/MIR/X86/undef-register-flag.mir
  test/CodeGen/MIR/X86/used-physical-register-info.mir
  test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
  test/CodeGen/MIR/X86/virtual-registers.mir
  test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
  test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
  test/CodeGen/PowerPC/stackmap-frame-setup.ll
  test/CodeGen/X86/eflags-copy-expansion.mir
  test/CodeGen/X86/expand-vr64-gr64-copy.mir
  test/CodeGen/X86/fixup-bw-copy.mir
  test/CodeGen/X86/fixup-bw-inst-fwlive.mir
  test/CodeGen/X86/implicit-null-checks.mir
  test/CodeGen/X86/machine-combiner-int.ll
  test/CodeGen/X86/machine-copy-prop.mir
  test/CodeGen/X86/patchpoint-verifiable.mir
  test/CodeGen/X86/pr27681.mir
  test/CodeGen/X86/stackmap-frame-setup.ll
  test/CodeGen/X86/update-terminator.mir
  test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll
  test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
  test/DebugInfo/MIR/X86/live-debug-values.mir
  test/DebugInfo/X86/bbjoin.ll
  test/DebugInfo/X86/float_const_loclist.ll
  test/DebugInfo/X86/safestack-byval.ll
  test/DebugInfo/X86/single-dbg_value.ll
  tools/llc/llc.cpp

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