[PATCH] D22042: [AArch64] Macro fusion of simple ALU ops with branches for Broadcom's Vulcan
Renato Golin via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 8 02:35:53 PDT 2016
rengolin added a comment.
In http://reviews.llvm.org/D22042#477752, @pgode wrote:
> I approached the table-gen option of adding instruction property, similar to adding CheapAsAMov property. In MCID(MCInstrDesc) Flags, there are already 32 flags, 'new flag MacroOpFusable' becomes the 33rd flag. Though Flags is 'uint64_t', still I see a warning message 'left shift count >= width of type'.
Hum, that's not good. We'll have to think about many of them, if we can turn them into properties, rather than features. There were some that could, maybe we need a larger re-factor than I was expecting.
> I am thinking of submitting a 'new diff' on this review by just enabling 'FeatureMacroOpFusion' (AArch64.td file modification) for Vulcan and let only ADDS, SUBS, ANDS get fused (default Subtarget feature behavior) and work on table-gen part for complete solution. Please suggest.
I think you're right. This is the pragmatic approach and will give us time to work out a better way forward.
More information about the llvm-commits