[llvm] r274818 - AMDGPU: Move si_mask_branch register operand to be a use

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Thu Jul  7 19:55:44 2016
New Revision: 274818

URL: http://llvm.org/viewvc/llvm-project?rev=274818&view=rev
Log:
AMDGPU: Move si_mask_branch register operand to be a use

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
    llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp?rev=274818&r1=274817&r2=274818&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp Thu Jul  7 19:55:44 2016
@@ -113,7 +113,7 @@ void AMDGPUAsmPrinter::EmitInstruction(c
         SmallVector<char, 16> BBStr;
         raw_svector_ostream Str(BBStr);
 
-        const MachineBasicBlock *MBB = MI->getOperand(1).getMBB();
+        const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
         const MCSymbolRefExpr *Expr
           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
         Expr->print(Str, MAI);

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=274818&r1=274817&r2=274818&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Thu Jul  7 19:55:44 2016
@@ -1929,7 +1929,7 @@ let hasSideEffects = 1, isPseudo = 1, is
 // Dummy terminator instruction to use after control flow instructions
 // replaced with exec mask operations.
 def SI_MASK_BRANCH : InstSI <
-  (outs SReg_64:$dst), (ins brtarget:$target)> {
+  (outs), (ins brtarget:$target, SReg_64:$dst)> {
   let isBranch = 1;
   let isTerminator = 1;
   let isBarrier = 1;

Modified: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=274818&r1=274817&r2=274818&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp Thu Jul  7 19:55:44 2016
@@ -237,8 +237,9 @@ void SILowerControlFlow::If(MachineInstr
   Skip(MI, MI.getOperand(2));
 
   // Insert a pseudo terminator to help keep the verifier happy.
-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Reg)
-    .addOperand(MI.getOperand(2));
+  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
+    .addOperand(MI.getOperand(2))
+    .addReg(Reg);
 
   MI.eraseFromParent();
 }
@@ -269,8 +270,9 @@ void SILowerControlFlow::Else(MachineIns
   Skip(MI, MI.getOperand(2));
 
   // Insert a pseudo terminator to help keep the verifier happy.
-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Dst)
-    .addOperand(MI.getOperand(2));
+  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
+    .addOperand(MI.getOperand(2))
+    .addReg(Dst);
 
   MI.eraseFromParent();
 }