[PATCH] D19825: Power9 - Add exploitation of vector load and store that do not require swaps
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 7 09:03:38 PDT 2016
nemanjai added inline comments.
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:10554
@@ -10550,3 +10553,3 @@
MVT StoreVT = VT.getSimpleVT();
- if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
+ if (NeedsSwapsForVSXMemOps &&
(StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
> Would it make sense for this to be a subtarget feature given all of the load/store instruction changes for vectors? Though I guess you couldn't just use Subtarget.isISA3_0 anymore as the canonical "am I targeting something P9 or later".
I can certainly define something like HasNonPermutingMemOps in PPC.td and make it part of the Power9 processor definition. The only reason it hasn't been defined is that we kind of decided not to have too much granularity with Power9 since there are no optional features. But if you feel that it might be useful to be able to turn this off and turn on the rest of the Power9 instructions, I can certainly do that.
More information about the llvm-commits