[PATCH] D22068: [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.

[Justin Lebar via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL274674: [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM. (authored by jlebar).

Changed prior to commit:
  http://reviews.llvm.org/D22068?vs=62958&id=62965#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D22068

Files:
  llvm/trunk/lib/Target/NVPTX/NVPTX.td
  llvm/trunk/test/CodeGen/NVPTX/sm-version-60.ll
  llvm/trunk/test/CodeGen/NVPTX/sm-version-61.ll
  llvm/trunk/test/CodeGen/NVPTX/sm-version-62.ll

Index: llvm/trunk/test/CodeGen/NVPTX/sm-version-61.ll
===================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-61.ll
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-61.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_61 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_61 | FileCheck %s
+
+; CHECK: .version 5.0
+; CHECK: .target sm_61
Index: llvm/trunk/test/CodeGen/NVPTX/sm-version-60.ll
===================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-60.ll
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-60.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_60 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
+
+; CHECK: .version 5.0
+; CHECK: .target sm_60
Index: llvm/trunk/test/CodeGen/NVPTX/sm-version-62.ll
===================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-62.ll
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-62.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_62 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_62 | FileCheck %s
+
+; CHECK: .version 5.0
+; CHECK: .target sm_62
Index: llvm/trunk/lib/Target/NVPTX/NVPTX.td
===================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTX.td
+++ llvm/trunk/lib/Target/NVPTX/NVPTX.td
@@ -44,6 +44,12 @@
                             "Target SM 5.2">;
 def SM53 : SubtargetFeature<"sm_53", "SmVersion", "53",
                             "Target SM 5.3">;
+def SM60 : SubtargetFeature<"sm_60", "SmVersion", "60",
+                             "Target SM 6.0">;
+def SM61 : SubtargetFeature<"sm_61", "SmVersion", "61",
+                             "Target SM 6.1">;
+def SM62 : SubtargetFeature<"sm_62", "SmVersion", "62",
+                             "Target SM 6.2">;
 
 // PTX Versions
 def PTX32 : SubtargetFeature<"ptx32", "PTXVersion", "32",
@@ -54,6 +60,10 @@
                              "Use PTX version 4.1">;
 def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42",
                              "Use PTX version 4.2">;
+def PTX43 : SubtargetFeature<"ptx43", "PTXVersion", "43",
+                             "Use PTX version 4.3">;
+def PTX50 : SubtargetFeature<"ptx50", "PTXVersion", "50",
+                             "Use PTX version 5.0">;
 
 //===----------------------------------------------------------------------===//
 // NVPTX supported processors.
@@ -71,7 +81,9 @@
 def : Proc<"sm_50", [SM50, PTX40]>;
 def : Proc<"sm_52", [SM52, PTX41]>;
 def : Proc<"sm_53", [SM53, PTX42]>;
-
+def : Proc<"sm_60", [SM60, PTX50]>;
+def : Proc<"sm_61", [SM61, PTX50]>;
+def : Proc<"sm_62", [SM62, PTX50]>;
 
 def NVPTXInstrInfo : InstrInfo {
 }


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