[PATCH] D21885: RegScavenging: Add scavengeRegisterBackwards()
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 6 10:42:28 PDT 2016
t.p.northover added a subscriber: t.p.northover.
Comment at: include/llvm/CodeGen/RegisterScavenging.h:168-169
@@ -165,1 +167,4 @@
+ /// Make a register of the specific register class available from the current
+ /// position to \p To (inclusive). SPAdj is the stack adjustment due to call
+ /// frame, it's passed along to eliminateFrameIndex(). Returns the scavenged
Could you be explicit about what the range is here?
I'm guessing `To` is before `this->MBBI` and that "inclusive" only applies to both, so the range would be `[To, this->MBBI]` (i.e. neither `To` nor `this->MBBI` may clobber the register).
Comment at: lib/CodeGen/PrologEpilogInserter.cpp:1169-1171
@@ +1168,5 @@
+ // The first definition writes the register, subsequent definitions are
+ // allowed but only if the instructions read+write the register (typical
+ // for two address code). Search for the first definition.
+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
I don't follow this 2-address exception. It looks like for something like
1: %v0 = INST %v0, ...
2: %v0 = INST
3: INST %v0<kill>
we'd find DefMI is instruction 2 and look for a register that's free between 2 & 3, but then set %v0 to this register everywhere. What happens if that register is defined between 1 & 2?
It seems unlikely that the first Def will be an instruction like 1 (though not impossible `and w0, w0, #0` or something could exist), but then again the whole exception is pointless if it can't happen.
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