[PATCH] D22026: AMDGPU: Expand register indexing pseudos in custom inserter

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm.

This is to help moveSILowerControlFlow to before regalloc.
There are a couple of tradeoffs with this. The complete CFG
is visible to more passes, the loop body avoids an extra copy of m0,
vcc isn't required, and immediate offsets can be shrunk into s_movk_i32.
    
The disadvantage is the register allocator doesn't understand that
the single lane's vector is dead within the loop body, so an extra
register is used to outlive the loop block when expanding the
VGPR -> m0 loop. This also now results in worse waitcnt insertion
before the loop instead of after for pending operations at the point
of the indexing, but that should be fixed by future improvements to
cross block waitcnt insertion.
    
v_movreld_b32's operands are now modeled more correctly since vdst
 is not a true output. This is kind of a hack to treat vdst as a
 use operand. Extra checking is required in the verifier since
I can't seem to get tablegen to emit an implicit operand for a
virtual register.

http://reviews.llvm.org/D22026

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SILowerControlFlow.cpp
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  test/CodeGen/AMDGPU/indirect-addressing-si.ll
  test/CodeGen/AMDGPU/indirect-addressing-undef.mir
  test/CodeGen/AMDGPU/insert_vector_elt.ll

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