[PATCH] D22008: GlobalISel: implement low-level type suitable for MachineInstr selection

Tim Northover via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 5 12:58:23 PDT 2016


t.p.northover created this revision.
t.p.northover added a reviewer: qcolombet.
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t.p.northover set the repository for this revision to rL LLVM.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: mcrosier, vkalintiris, mehdi_amini.

In my first attempt at a legalization framework for GlobalISel (http://reviews.llvm.org/D21534), Quentin said he intended to move towards a lower-level type representation (essentially just size & lanes). Since the legalization description makes heavy use of types, it's probably best to do that earlier rather than later, hence this patch.

I've added a new ``LLT`` class, with 3 variants, designed to look similar to IR-level types:

  * ``unsized`` for labels etc
  * ``sN`` for scalars & aggregates.
  * ``<N x sM>`` for vectors.

At the moment, vectors must contain more than 1 element (so no ``<1 x double>``). I know there are doubts about this being adequate, but I'd like to press on as far as possible under the assumption that RegBankSelect can handle things and it's easier to relax that requirement than impose it later if we're wrong.

There should be no functional change here (we still don't have that much functionality to change!). Test changes are just updating to the new syntax.

Cheers.

Tim.

Repository:
  rL LLVM

http://reviews.llvm.org/D22008

Files:
  include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
  include/llvm/CodeGen/LowLevelType.h
  include/llvm/CodeGen/MachineInstr.h
  lib/CodeGen/CMakeLists.txt
  lib/CodeGen/GlobalISel/IRTranslator.cpp
  lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  lib/CodeGen/LowLevelType.cpp
  lib/CodeGen/MIRParser/MILexer.cpp
  lib/CodeGen/MIRParser/MILexer.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  lib/Target/AArch64/AArch64RegisterBankInfo.h
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
  test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
  test/CodeGen/MIR/X86/generic-instr-type-error.mir
  test/CodeGen/MIR/X86/generic-virtual-registers.mir

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