[llvm] r274381 - [Hexagon] Use MachineOperand::readsReg instead of isUse

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Jul  1 15:28:30 2016
New Revision: 274381

URL: http://llvm.org/viewvc/llvm-project?rev=274381&view=rev
Log:
[Hexagon] Use MachineOperand::readsReg instead of isUse

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=274381&r1=274380&r2=274381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Fri Jul  1 15:28:30 2016
@@ -349,7 +349,7 @@ void HexagonExpandCondsets::updateKillFl
     // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
     MachineInstr *MI = LIS->getInstructionFromIndex(K);
     for (auto &Op : MI->operands()) {
-      if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
+      if (!Op.isReg() || !Op.readsReg() || Op.getReg() != Reg)
         continue;
       LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
       if ((SLM & LM) == SLM) {