[PATCH] D21802: Ensure all uses of permute instruction feed vector stores

[Nemanja Ivanovic via llvm-commits]

nemanjai added a comment.

In http://reviews.llvm.org/D21802#469887, @wschmidt wrote:

> The patch LGTM.  One question: Did you check for the reverse situation?  Can we have a swap that is fed by more than one instruction, where one is not a load, or is that already handled in the code?  I realize this may not come up in practice if we don't have a machine sinking pass.
>
> @nemanjai, yes, you could disable other optimizations, but I wouldn't recommend it.  If one were going to spend more time on swap optimization, I'd instead recommend optimizing the web but inserting swaps in specific cases like this where something other than an STXVD2X occurs, which would always be a win in practice (though you could construct pathological cases where the code could get larger, though still no slower).  But since http://reviews.llvm.org/P8 optimization is off the table right now, I'd just leave things lie.


Excellent, thanks for answering the question Bill. I really only asked it because I don't know enough about this to know if allowing MachineCSE to eliminate swaps might lead to other situations where we do the wrong thing in our pass.


http://reviews.llvm.org/D21802