[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Evandro Menezes via llvm-commits]

evandro added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64.td:96
@@ -93,1 +95,3 @@
+    "Do not generate indexed vector instructions">;
+
 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
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The ISA manual refers to such operations as "vector by element", so I'd prefer something like 's/VectorIndexing/VectorByElement/'.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:311
@@ -310,2 +310,3 @@
 def NotForCodeSize   : Predicate<"!ForCodeSize">;
+def VectorIndexing : Predicate<"!Subtarget->avoidVectorIndexing()">;
 
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s/Indexing/ByElement/

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Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.h:82
@@ -81,2 +81,3 @@
   bool AvoidQuadLdStPairs = false;
+  bool AvoidVectorIndexing = false;
   bool UseAlternateSExtLoadCVTF32Pattern = false;
----------------
s/Indexing/ByElement/

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Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.h:189
@@ -187,2 +188,3 @@
   bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }
+  bool avoidVectorIndexing() const { return AvoidVectorIndexing; }
   bool useAlternateSExtLoadCVTF32Pattern() const {
----------------
s/Indexing/ByElement/

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Comment at: llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll:2
@@ -1,2 +1,3 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
 
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Refrain from setting the CPU in tests.  Rather, use the feature that you added with "-mattr=no-vector-instruction-indexing", or rather, "-mattr=no-vector-by-element"


http://reviews.llvm.org/D21571