[PATCH] D21578: [SelectionDAG] Optimization of BITREVERSE legalization for power-of-2 integer scalar/vector types

[Sanjay Patel via llvm-commits]

spatel added a comment.

I haven't looked at bitreverse before this, so James or someone else should review too. A few nits inline, but otherwise LGTM.

Is there something that guarantees that an i2 or i4 type doesn't get in here? Should we assert that VT is i8 or larger?

BTW,  there's a bug in the LangRef:
"The llvm.bitreverse.iN intrinsic returns an i16 value"


================
Comment at: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2560
@@ -2559,3 +2559,3 @@
 
 /// Open code the operations for BITREVERSE.
 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
----------------
Open code?

================
Comment at: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2568-2569
@@ +2567,4 @@
+
+  // If we can perform BSWAP first and then perform the mask+swap the i4, then i2
+  // and finally the i1 pairs.
+  if (isPowerOf2_32(Sz)) {
----------------
If I'm reading this sentence correctly, it should be:
"If we can, perform"

================
Comment at: test/CodeGen/X86/vector-bitreverse.ll:16
@@ -14,27 +15,3 @@
 ; SSE-NEXT:    movl %edi, %eax
-; SSE-NEXT:    shlb $7, %al
-; SSE-NEXT:    movl %edi, %ecx
-; SSE-NEXT:    shlb $5, %cl
-; SSE-NEXT:    andb $64, %cl
-; SSE-NEXT:    movl %edi, %edx
-; SSE-NEXT:    shlb $3, %dl
-; SSE-NEXT:    andb $32, %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    movl %edi, %ecx
-; SSE-NEXT:    addb %cl, %cl
-; SSE-NEXT:    andb $16, %cl
-; SSE-NEXT:    orb %dl, %cl
-; SSE-NEXT:    movl %edi, %edx
-; SSE-NEXT:    shrb %dl
-; SSE-NEXT:    andb $8, %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    movl %edi, %ecx
-; SSE-NEXT:    shrb $3, %cl
-; SSE-NEXT:    andb $4, %cl
-; SSE-NEXT:    orb %dl, %cl
-; SSE-NEXT:    movl %edi, %edx
-; SSE-NEXT:    shrb $5, %dl
-; SSE-NEXT:    andb $2, %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    shrb $7, %dil
-; SSE-NEXT:    orb %dl, %dil
+; SSE-NEXT:    andb $51, %al
+; SSE-NEXT:    shlb $2, %al
----------------
I wish we printed hex asm comments for 8-bit immediates too. :)


Repository:
  rL LLVM

http://reviews.llvm.org/D21578