[llvm] r273172 - AMDGPU: Use correct method for determining instruction size

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Jun 20 12:51:32 2016
New Revision: 273172

URL: http://llvm.org/viewvc/llvm-project?rev=273172&view=rev
Log:
AMDGPU: Use correct method for determining instruction size

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=273172&r1=273171&r2=273172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Mon Jun 20 12:51:32 2016
@@ -28,6 +28,7 @@
 #include "R600RegisterInfo.h"
 #include "SIDefines.h"
 #include "SIMachineFunctionInfo.h"
+#include "SIInstrInfo.h"
 #include "SIRegisterInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/MC/MCContext.h"
@@ -309,6 +310,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(
   bool FlatUsed = false;
   const SIRegisterInfo *RI =
       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
+  const SIInstrInfo *TII =
+      static_cast<const SIInstrInfo *>(STM.getInstrInfo());
 
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
@@ -318,8 +321,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(
       if (MI.isDebugValue())
         continue;
 
-      // FIXME: This is reporting 0 for many instructions.
-      CodeSize += MI.getDesc().Size;
+      CodeSize += TII->getInstSizeInBytes(MI);
 
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {

Modified: llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll?rev=273172&r1=273171&r2=273172&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll Mon Jun 20 12:51:32 2016
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
 
-; CHECK: {{^}}inline_asm:
+; CHECK-LABEL: {{^}}inline_asm:
 ; CHECK: s_endpgm
 ; CHECK: s_endpgm
 define void @inline_asm(i32 addrspace(1)* %out) {
@@ -11,7 +11,7 @@ entry:
   ret void
 }
 
-; CHECK: {{^}}inline_asm_shader:
+; CHECK-LABEL: {{^}}inline_asm_shader:
 ; CHECK: s_endpgm
 ; CHECK: s_endpgm
 define amdgpu_ps void @inline_asm_shader() {
@@ -38,7 +38,7 @@ endif:
   ret void
 }
 
-; CHECK: {{^}}v_cmp_asm:
+; CHECK-LABEL: {{^}}v_cmp_asm:
 ; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
 ; CHECK: v_cmp_ne_i32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]]
 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
@@ -49,3 +49,31 @@ define void @v_cmp_asm(i64 addrspace(1)*
   store i64 %sgpr, i64 addrspace(1)* %out
   ret void
 }
+
+; CHECK-LABEL: {{^}}code_size_inline_asm:
+; CHECK: codeLenInByte = 12
+define void @code_size_inline_asm(i32 addrspace(1)* %out) {
+entry:
+  call void asm sideeffect "v_nop_e64", ""()
+  ret void
+}
+
+; All inlineasm instructions are assumed to be the maximum size
+; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst:
+; CHECK: codeLenInByte = 12
+define void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) {
+entry:
+  call void asm sideeffect "v_nop_e32", ""()
+  ret void
+}
+
+; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst:
+; CHECK: codeLenInByte = 20
+define void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) {
+entry:
+  call void asm sideeffect "
+    v_nop_e64
+    v_nop_e64
+   ", ""()
+  ret void
+}