[llvm] r273166 - AMDGPU: Emit R_AMDGPU_ABS32_{HI, LO} for scratch buffer relocations

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Mon Jun 20 11:59:44 2016
New Revision: 273166

URL: http://llvm.org/viewvc/llvm-project?rev=273166&view=rev
Log:
AMDGPU: Emit R_AMDGPU_ABS32_{HI,LO} for scratch buffer relocations

Reviewers: arsenm, rafael, kzhuravl

Subscribers: rafael, arsenm, llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D21400

Added:
    llvm/trunk/test/MC/AMDGPU/reloc.s
Modified:
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
    llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp?rev=273166&r1=273165&r2=273166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp Mon Jun 20 11:59:44 2016
@@ -21,10 +21,7 @@ public:
   AMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend);
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
-                        const MCFixup &Fixup, bool IsPCRel) const override {
-    return Fixup.getKind();
-  }
-
+                        const MCFixup &Fixup, bool IsPCRel) const override;
 };
 
 
@@ -37,6 +34,20 @@ AMDGPUELFObjectWriter::AMDGPUELFObjectWr
                             ELF::EM_AMDGPU,
                             HasRelocationAddend) { }
 
+unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
+                                             const MCValue &Target,
+                                             const MCFixup &Fixup,
+                                             bool IsPCRel) const {
+  // SCRATCH_RSRC_DWORD[01] is a special global variable that represents
+  // the scratch buffer.
+  if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD0")
+    return ELF::R_AMDGPU_ABS32_LO;
+  if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
+    return ELF::R_AMDGPU_ABS32_HI;
+
+  llvm_unreachable("unhandled relocation type");
+}
+
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,
                                                   bool HasRelocationAddend,

Modified: llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll?rev=273166&r1=273165&r2=273166&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll Mon Jun 20 11:59:44 2016
@@ -8,9 +8,9 @@
 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
 
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
-; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0, kind: FK_Data_4
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
-; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1, kind: FK_Data_4
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000
 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000

Added: llvm/trunk/test/MC/AMDGPU/reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/reloc.s?rev=273166&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/reloc.s (added)
+++ llvm/trunk/test/MC/AMDGPU/reloc.s Mon Jun 20 11:59:44 2016
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations | FileCheck %s
+
+// CHECK: Relocations [
+// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
+// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
+// CHECK: ]
+
+kernel:
+  s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+  s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+
+.globl SCRATCH_RSRC_DWORD0