[PATCH] D20830: Fix branch relaxation in 16-bit mode.

[Nirav Dave via llvm-commits]

niravd added a comment.

In http://reviews.llvm.org/D20830#461914, @craig.topper wrote:

> Are there cases where 16-bit mode may need a full 32-bit offset that we need to support here? Or would that wrap the segment boundary for 16-bit mode and be illegal?


Yes, since EIP calculation is always truncated to 16-bit so we can safely truncate our offset in the instruction and none of the exception checks make use of the top 16-bits of the 32-bit new EIP so it should always be okay to do the 16-bit truncated calculation in lieu of the 32-bit one.


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Comment at: lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:138
@@ -137,2 +137,3 @@
 
-static unsigned getRelaxedOpcodeBranch(unsigned Op) {
+static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) {
+  unsigned Op = Inst.getOpcode();
----------------
craig.topper wrote:
> Why are we no longer passing just the Opcode to this function?
It was to make branch and arithmetic relaxation procedures more similar in shape as they're clearly related. Having them both take Opcode would work equally as well.


http://reviews.llvm.org/D20830