[PATCH] D20379: Codegen: Fix broken assumption in Tail Merge.

[Eli Friedman via llvm-commits]

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eli.friedman added a comment.

Err, are you talking about https://github.com/llvm-mirror/llvm/blob/961fcb527d3c49bfcf9d6ff212cca3dc15682dbe/lib/CodeGen/MachineLICM.cpp#L869 ?  You can't write a constant pool load in IR. You can write something like `store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32*> @g`, and SelectionDAG will generate a constant pool load.


http://reviews.llvm.org/D20379