[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

Chuang-Yu Cheng via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 14 02:35:28 PDT 2016

cycheng added a comment.

Eliminating VSHRC brought up a new issue for me, but **I have fixed it**. Tom will upload the new patch later (the patch passed all of my testing on Pwr8).

The issue was:
Because for now, VSRC = (VSLRC, VRRC), so when spill vs0-63 or vr0-31 to stack, backend was possible to generate such code:

  STXVD2X %VSL11<kill>, %X31, %X0<kill>, %RM<imp-use>; mem:ST16[FixedStack17]
  %V3<def> = LVX %X31, %X0<kill>; mem:LD16[FixedStack17]

We spill vs11 by **STXVD2X**, but we reload it to vr3 by **LVX**.

Such test case is rare,  I hit the issue when I was running 453.povray

  // in texture.cpp, InitTextureTable()
  int i;
  for (i = 0; i < 4096; i++)
    hashTable[i] = i;

This simple for loop was translated into more than **1,000 lines** assembly code //(by the way, I thought the inefficient code gen here was related to non-legal vector type legalization that Nemanjai is fixing)//

A lot of vmx and vsx registers were used, altivec and vsx instructions were interleaved, then we hit this issue.


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