[PATCH] D20239: [Power9] Add codegen for VSX word insert/extract instructions

Nemanja Ivanovic via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 13 10:55:57 PDT 2016

nemanjai added inline comments.

Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:1566-1567
@@ +1565,4 @@
+  // If both vector operands for the shuffle are the same vector, the mask will
+  // contain only elements from the first one and the second one will be undef.
+  if (N->getOperand(1).isUndef()) {
nemanjai wrote:
> amehsan wrote:
> > How is this guaranteed?
> It is not guaranteed. It is just what Clang does (and presumably other transformations don't break it). Sure, we could provide code here that handles bizarre cases where a shuffle is performed and both vector operands are the same. However, I don't believe such code will be the output of any sane transformation as absolutely no further information is gained by having two of the same operands vs. having one operand be undef. So adding special code to handle this is probably overkill - but if I'm wrong about this, I'm happy to add code to handle this.
I should correct that statement. I don't know whether this is guaranteed. Certainly, when I feed a test case with a repeated vector operand to llc, the initial selection DAG already contains that vector as the first operand and undef as the second operand. Consider this:

%vecins = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>


t4: v4i32 = vector_shuffle<0,2,2,3> t2, undef:v4i32



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