[llvm] r272450 - [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This allows us to create 512-bit PSHUFLW/PSHUFHW.

Sat Jun 11 08:05:08 PDT 2016

Hello Craig,

It looks like one of your recent commits broke the green dragon bots. Could you please take a look?

http://lab.llvm.org:8080/green//job/clang-stage1-cmake-RA-incremental_check/24682/consoleFull#13902200628254eaf0-7326-4999-85b0-388101f2d404

Thanks,
Adrian

> On Jun 10, 2016, at 8:27 PM, Craig Topper via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: ctopper
> Date: Fri Jun 10 22:27:42 2016
> New Revision: 272450
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=272450&view=rev
> Log:
> [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This allows us to create 512-bit PSHUFLW/PSHUFHW.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=272450&r1=272449&r2=272450&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 10 22:27:42 2016
> @@ -11827,6 +11827,17 @@ static SDValue lowerV32I16VectorShuffle(
>           DL, MVT::v32i16, V1, V2, Mask, Subtarget, DAG))
>     return Rotate;
> 
> +  if (isSingleInputShuffleMask(Mask)) {
> +    SmallVector<int, 8> RepeatedMask;
> +    if (is128BitLaneRepeatedShuffleMask(MVT::v32i16, Mask, RepeatedMask)) {
> +      // As this is a single-input shuffle, the repeated mask should be
> +      // a strictly valid v8i16 mask that we can pass through to the v8i16
> +      // lowering to handle even the v32 case.
> +      return lowerV8I16GeneralSingleInputVectorShuffle(
> +          DL, MVT::v32i16, V1, RepeatedMask, Subtarget, DAG);
> +    }
> +  }
> +
>   return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
> }
> 
> 
> Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll?rev=272450&r1=272449&r2=272450&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll Fri Jun 10 22:27:42 2016
> @@ -1,4 +1,4 @@
> -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
> ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
> 
> target triple = "x86_64-unknown-unknown"
> @@ -79,3 +79,31 @@ define <32 x i16> @shuffle_v32i16_z_0_z_
>   %c = shufflevector <32 x i16> %a, <32 x i16> zeroinitializer, <32 x i32> <i32 34, i32 0, i32 34, i32 2, i32 34, i32 4, i32 34, i32 6, i32 34, i32 8, i32 34, i32 10, i32 34, i32 12, i32 34, i32 14, i32 34, i32 16, i32 34, i32 18, i32 34, i32 20, i32 34, i32 22, i32 34, i32 24, i32 34, i32 26, i32 34, i32 28, i32 34, i32 30>
>   ret <32 x i16> %c
> }
> +
> +define <32 x i16> @shuffle_v32i16_1_1_0_0_4_5_6_7_9_9_8_8_12_13_14_15_17_17_16_16_20_21_22_23_25_25_24_24_28_29_30_31(<32 x i16> %a, <32 x i16> %b)  {
> +; ALL-LABEL: shuffle_v32i16_1_1_0_0_4_5_6_7_9_9_8_8_12_13_14_15_17_17_16_16_20_21_22_23_25_25_24_24_28_29_30_31:
> +; ALL:       # BB#0:
> +; ALL-NEXT:    vpshuflw {{.*#+}} zmm0 = zmm0[1,1,0,0,4,5,6,7,9,9,8,8,12,13,14,15,17,17,16,16,20,21,22,23,25,25,24,24,28,29,30,31]
> +; ALL-NEXT:    retq
> +  %c = shufflevector <32 x i16> %a, <32 x i16> zeroinitializer, <32 x i32> <i32 1, i32 1, i32 0, i32 0, i32 4, i32 5, i32 6, i32 7, i32 9, i32 9, i32 8, i32 8, i32 12, i32 13, i32 14, i32 15, i32 17, i32 17, i32 16, i32 16, i32 20, i32 21, i32 22, i32 23, i32 25, i32 25, i32 24, i32 24, i32 28, i32 29, i32 30, i32 31>
> +  ret <32 x i16> %c
> +}
> +
> +define <32 x i16> @shuffle_v32i16_0_1_2_3_5_5_4_4_8_9_10_11_13_13_12_12_16_17_18_19_21_21_20_20_24_25_26_27_29_29_28_28(<32 x i16> %a, <32 x i16> %b)  {
> +; ALL-LABEL: shuffle_v32i16_0_1_2_3_5_5_4_4_8_9_10_11_13_13_12_12_16_17_18_19_21_21_20_20_24_25_26_27_29_29_28_28:
> +; ALL:       # BB#0:
> +; ALL-NEXT:    vpshufhw {{.*#+}} zmm0 = zmm0[0,1,2,3,5,5,4,4,8,9,10,11,13,13,12,12,16,17,18,19,21,21,20,20,24,25,26,27,29,29,28,28]
> +; ALL-NEXT:    retq
> +  %c = shufflevector <32 x i16> %a, <32 x i16> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 5, i32 4, i32 4, i32 8, i32 9, i32 10, i32 11, i32 13, i32 13, i32 12, i32 12, i32 16, i32 17, i32 18, i32 19, i32 21, i32 21, i32 20, i32 20, i32 24, i32 25, i32 26, i32 27, i32 29, i32 29, i32 28, i32 28>
> +  ret <32 x i16> %c
> +}
> +
> +define <32 x i16> @shuffle_v32i16_1_1_0_0_5_5_4_4_9_9_11_11_13_13_12_12_17_17_19_19_21_21_20_20_25_25_27_27_29_29_28_28(<32 x i16> %a, <32 x i16> %b)  {
> +; ALL-LABEL: shuffle_v32i16_1_1_0_0_5_5_4_4_9_9_11_11_13_13_12_12_17_17_19_19_21_21_20_20_25_25_27_27_29_29_28_28:
> +; ALL:       # BB#0:
> +; ALL-NEXT:    vpshuflw {{.*#+}} zmm0 = zmm0[1,1,0,0,4,5,6,7,9,9,8,8,12,13,14,15,17,17,16,16,20,21,22,23,25,25,24,24,28,29,30,31]
> +; ALL-NEXT:    vpshufhw {{.*#+}} zmm0 = zmm0[0,1,2,3,5,5,4,4,8,9,10,11,13,13,12,12,16,17,18,19,21,21,20,20,24,25,26,27,29,29,28,28]
> +; ALL-NEXT:    retq
> +  %c = shufflevector <32 x i16> %a, <32 x i16> zeroinitializer, <32 x i32> <i32 1, i32 1, i32 0, i32 0, i32 5, i32 5, i32 4, i32 4, i32 9, i32 9, i32 8, i32 8, i32 13, i32 13, i32 12, i32 12, i32 17, i32 17, i32 16, i32 16, i32 21, i32 21, i32 20, i32 20, i32 25, i32 25, i32 24, i32 24, i32 29, i32 29, i32 28, i32 28>
> +  ret <32 x i16> %c
> +}
> 
> 
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