[PATCH] D21153: AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL272417: AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations (authored by tstellar).

Changed prior to commit:
  http://reviews.llvm.org/D21153?vs=60102&id=60388#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D21153

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
  llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll

Index: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -249,7 +249,12 @@
 
   if (MO.isExpr()) {
     const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
-    MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
+    const MCSymbol &Sym = Expr->getSymbol();
+    MCFixupKind Kind;
+    if (Sym.isExternal())
+      Kind = FK_Data_4;
+    else
+      Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
     Fixups.push_back(MCFixup::create(4, Expr, Kind, MI.getLoc()));
   }
 
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -75,6 +75,7 @@
     }
     case MachineOperand::MO_ExternalSymbol: {
       MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
+      Sym->setExternal(true);
       const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
       MCOp = MCOperand::createExpr(Expr);
       break;
Index: llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/large-alloca-compute.ll
@@ -1,14 +1,16 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
-; RUN: llc -march=amdgcn -mcpu=carrizo < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
+; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
 
 ; FIXME: align on alloca seems to be ignored for private_segment_alignment
 
 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
 
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0, kind: FK_Data_4
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1, kind: FK_Data_4
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0x88f000
 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0x880000


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