[PATCH] D16917: [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

[Hrvoje Varga via llvm-commits]

hvarga updated this revision to Diff 60154.
hvarga added a comment.

Added MM64R6 cases to LowerLargeShift and encodeInstruction for DSLL, DSRA and DROTR instructions.
Instruction mapping tables:

  Added StdMMR6Rel to DSLL, DSRA, DCLO, and DCLZ Mips64 instructions.
  Added R6MMR6Rel to DCLO and DCLZ Mips64R6 instructions.

Joined NotInMicroMips predicate blocks where possible.

This update has been contributed by @mamidzic.


http://reviews.llvm.org/D16917

Files:
  lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
  lib/Target/Mips/MicroMips64r6InstrFormats.td
  lib/Target/Mips/MicroMips64r6InstrInfo.td
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/Mips64r6InstrInfo.td
  test/CodeGen/Mips/countleading.ll
  test/CodeGen/Mips/mips64shift.ll
  test/MC/Disassembler/Mips/micromips64r6/valid.txt
  test/MC/Mips/micromips64r6/invalid.s
  test/MC/Mips/micromips64r6/valid.s

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