[llvm] r272226 - [MIR] Check that generic virtual registers get a size.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Wed Jun  8 18:27:46 2016
New Revision: 272226

URL: http://llvm.org/viewvc/llvm-project?rev=272226&view=rev
Log:
[MIR] Check that generic virtual registers get a size.

Without that check it was possible to write test cases where the size
was not specified and we ended up with weird asserts down the road,
because the default value (1) would not make sense.

Added:
    llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
Modified:
    llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
    llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
    llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp

Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=272226&r1=272225&r2=272226&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Wed Jun  8 18:27:46 2016
@@ -970,10 +970,7 @@ bool MIParser::parseRegisterOperand(Mach
       TiedDefIdx = Idx;
     }
   } else if (consumeIfPresent(MIToken::lparen)) {
-    // Generic virtual registers must have a size.
-    // The "must" part will be verify by the machine verifier,
-    // because at this point we actually do not know if Reg is
-    // a generic virtual register.
+    // Virtual registers may have a size with GlobalISel.
     if (!TargetRegisterInfo::isVirtualRegister(Reg))
       return error("unexpected size on physical register");
     unsigned Size;
@@ -982,6 +979,11 @@ bool MIParser::parseRegisterOperand(Mach
 
     MachineRegisterInfo &MRI = MF.getRegInfo();
     MRI.setSize(Reg, Size);
+  } else if (PFS.GenericVRegs.count(Reg)) {
+    // Generic virtual registers must have a size.
+    // If we end up here this means the size hasn't been specified and
+    // this is bad!
+    return error("generic virtual registers must have a size");
   }
   Dest = MachineOperand::CreateReg(
       Reg, Flags & RegState::Define, Flags & RegState::Implicit,

Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=272226&r1=272225&r2=272226&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.h Wed Jun  8 18:27:46 2016
@@ -15,6 +15,7 @@
 #define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
 
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
 
 namespace llvm {
 
@@ -35,6 +36,8 @@ struct PerFunctionMIParsingState {
   DenseMap<unsigned, int> StackObjectSlots;
   DenseMap<unsigned, unsigned> ConstantPoolSlots;
   DenseMap<unsigned, unsigned> JumpTableSlots;
+  /// Hold the generic virtual registers.
+  SmallSet<unsigned, 8> GenericVRegs;
 };
 
 /// Parse the machine basic block definitions, and skip the machine

Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=272226&r1=272225&r2=272226&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Wed Jun  8 18:27:46 2016
@@ -365,6 +365,7 @@ bool MIRParserImpl::initializeRegisterIn
       // This is a generic virtual register.
       // The size will be set appropriately when we reach the definition.
       Reg = RegInfo.createGenericVirtualRegister(/*Size*/ 1);
+      PFS.GenericVRegs.insert(Reg);
     } else {
       const auto *RC = getRegClass(MF, VReg.Class.Value);
       if (RC) {
@@ -378,6 +379,7 @@ bool MIRParserImpl::initializeRegisterIn
                   VReg.Class.Value + "'");
         Reg = RegInfo.createGenericVirtualRegister(/*Size*/ 1);
         RegInfo.setRegBank(Reg, *RegBank);
+        PFS.GenericVRegs.insert(Reg);
       }
     }
     if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))

Added: llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir?rev=272226&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir Wed Jun  8 18:27:46 2016
@@ -0,0 +1,44 @@
+# RUN: not llc -mtriple=aarch64-apple-ios -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2> %t.log
+# Everything is written on STDERR with mir, which is bad. So make two runs for now.
+# RUN: FileCheck %s -input-file=%t.log --check-prefix=CHECK
+# RUN: FileCheck %s -input-file=%t.log --check-prefix=ERR
+# RUN: rm -f %t.log
+# REQUIRES: global-isel
+# This test ensures that the MIR parser errors out when
+# generic virtual register definitions are not correct.
+
+--- |
+  define void @bar() { ret void }
+
+  define void @baz() { ret void }
+...
+
+---
+name:            bar
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: gpr }
+registers:
+  - { id: 0, class: gpr }
+body: |
+  bb.0:
+    liveins: %w0
+    ; ERR: generic virtual registers must have a size
+    ; ERR-NEXT: %0
+    %0 = G_ADD i32 %w0, %w0
+...
+
+---
+name:            baz
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: _ }
+registers:
+  - { id: 0, class: _ }
+body: |
+  bb.0:
+    liveins: %w0
+    ; ERR: generic virtual registers must have a size
+    ; ERR-NEXT: %0
+    %0 = G_ADD i32 %w0, %w0
+...