[llvm] r272122 - [AVX512] Fix cvtusi2sd instruction Opcode, it should be 0x7B instead of 0x2A.

[Igor Breger via llvm-commits]

Author: ibreger
Date: Wed Jun  8 02:48:23 2016
New Revision: 272122

URL: http://llvm.org/viewvc/llvm-project?rev=272122&view=rev
Log:
[AVX512] Fix cvtusi2sd instruction Opcode, it should be 0x7B instead of 0x2A.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td

Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=272122&r1=272121&r2=272122&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Wed Jun  8 02:48:23 2016
@@ -5097,7 +5097,7 @@ let isCodeGenOnly = 1 , Predicates = [Ha
             int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
             SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
 
-  defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
+  defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x7B, GR32, VR128X,
             int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
             SSE_CVT_Scalar, 0>, XD, EVEX_4V;
 } // isCodeGenOnly = 1, Predicates = [HasAVX512]