[PATCH] D20931: [X86] Reduce the width of multiplification when its operands are extended from i8 or i16

Eli Friedman via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 7 17:22:18 PDT 2016

eli.friedman added inline comments.

Comment at: lib/Target/X86/X86ISelLowering.cpp:26506
@@ +26505,3 @@
+        bool IsNegative = CN->getAPIntValue().isNegative();
+        SbitsNum = DAG.ComputeNumSignBits(SubOp);
+        if (SbitsNum < 25)
It's probably more clear to express this in terms of the number of sign bits and the number of leading zeros (APInt::countLeadingZeros).  Actually, you could probably get rid of the ValRange enumeration altogether in favor of those two numbers.  For example, return `MULS8` if `std::min(signbits1, signbits2) > 24`.

Comment at: lib/Target/X86/X86ISelLowering.cpp:26675
@@ +26674,3 @@
+      return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
+                         DAG.getIntPtrConstant(0, DL));
+    } else {
I'm not following... how do you get to <4 x i64>?  Legalization of a `<4 x i16>` multiply will widen it to an `<8 x i16>` multiply; this codepath already gets used for IR like `mul <4 x i16> %a, %b`.



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